|
|
| Chair |
|
Minoru Watanabe (Shizuoka Univ.) |
| Vice Chair |
|
Masato Motomura (Hokkaido Univ.), Yuichiro Shibata (Nagasaki Univ.) |
| Secretary |
|
Yoshiki Yamaguchi (Univ. of Tsukuba), Kazuya Tanigawa (Hiroshima City Univ.) |
| Assistant |
|
Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC) |
|
| Conference Date |
Mon, Sep 5, 2016 13:10 - 17:25
Tue, Sep 6, 2016 09:10 - 14:40 |
| Topics |
Reconfigurable Systems, etc. |
| Conference Place |
Toyama University |
Contact
Person |
e-trees.Japan, Inc, Takefumi MIYOSHI |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
Mon, Sep 5 PM Applications (1)
13:10 - 14:25 |
| (1) |
13:10-13:35 |
Functional Improvement of cReComp Design Tool for Software-Component Generation of FPGA Processing  RECONF2016-24 |
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) |
| (2) |
13:35-14:00 |
RECONF2016-25 |
|
| (3) |
14:00-14:25 |
[Short Paper]
Study and Evaluation of FPGA based I/O Accelerator for the Flash Storage RECONF2016-26 |
Kazushi Nakagawa, Shotaro Shintani, Hirotoshi Akaike, Kentaro Shimada (Hitachi) |
| |
14:25-14:35 |
Break ( 10 min. ) |
Mon, Sep 5 PM High Level Synthesis
14:35 - 15:25 |
| (4) |
14:35-15:00 |
The effect of the C ++ template meta-programming in high-level synthesis RECONF2016-27 |
Kenichiro Mitsuda, Owada Hiroshi, Shinji Yamamoto (ISP) |
| (5) |
15:00-15:25 |
RECONF2016-28 |
|
| |
15:25-15:35 |
Break ( 10 min. ) |
Mon, Sep 5 PM Place and Route
15:35 - 16:25 |
| (6) |
15:35-16:00 |
Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT RECONF2016-29 |
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shoto Tamai (Oi Electric), Takumi Sato (Shonan Inst. of Tech.) |
| (7) |
16:00-16:25 |
RECONF2016-30 |
Tomohiro Tanaka, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (Taiyo Yuden) |
| |
16:25-16:35 |
Break ( 10 min. ) |
Mon, Sep 5 PM Invited Talk (1)
16:35 - 17:25 |
| (8) |
16:35-17:25 |
[Invited Talk]
Verification and Debugging Support Techniques for High-Level Designs RECONF2016-31 |
Takeshi Matsumoto (INCT) |
Tue, Sep 6 AM Invited Talk (2)
09:10 - 10:00 |
| (9) |
09:10-10:00 |
[Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture RECONF2016-32 |
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) |
| |
10:00-10:30 |
Break ( 30 min. ) |
Tue, Sep 6 AM Platform
10:30 - 11:45 |
| (10) |
10:30-10:55 |
Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board RECONF2016-33 |
Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science) |
| (11) |
10:55-11:20 |
A Study of Methodology and Tools for Open-source FPGA Accelerators RECONF2016-34 |
Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| (12) |
11:20-11:45 |
RECONF2016-35 |
|
| |
11:45-13:00 |
Break ( 75 min. ) |
Tue, Sep 6 PM Applications (2)
13:00 - 14:40 |
| (13) |
13:00-13:25 |
A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL RECONF2016-36 |
Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, Shinpei Sato (TITECH), Naoya Maruyama (RIKEN) |
| (14) |
13:25-13:50 |
A Memory Based Realization of the Binarized Deep Convolutional Neural Network RECONF2016-37 |
Hiroki Nakahara, Haruyoshi Yonekawa (TITECH), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (Poco a poco Networks), Masato Motomura (Hokkaido Univ.) |
| (15) |
13:50-14:15 |
An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation RECONF2016-38 |
Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) |
| (16) |
14:15-14:40 |
RECONF2016-39 |
|
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Inquiries for RECONF
Minoru Watanabe (Shizuoka University)
tm  n ipc    
Inquiries for the Meeting in May 2016
Takefumi MIYOSHI (e-trees.Japan, Inc.)
    n |
Last modified: 2016-08-27 13:44:27
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