|
|
| Chair |
|
Toshiyuki Shibuya (Fujitsu Labs.) |
| Vice Chair |
|
Yusuke Matsunaga (Kyushu Univ.) |
| Secretary |
|
Noriyuki Minegishi (Mitsubishi Electric), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
| Assistant |
|
Takehiro Miyazawa (MMS), Ryo Yamamoto (Mitsubishi Electric) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Masahiro Fukui (Ritsumeikan Univ.) |
| Secretary |
|
Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.), Masao Yokoyama (Sharp) |
|
| Conference Date |
Thu, May 14, 2015 09:15 - 15:50 |
| Topics |
System Design, etc. |
| Conference Place |
Kitakyushu International Conference Center |
Contact
Person |
Prof. Shigetoshi Nakatake |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, May 14 AM
09:15 - 10:30 |
(1)
VLD |
09:15-09:40 |
A minimum test pattern set generation for large circuits  VLD2015-1 |
Yusuke Matsunaga (Kyushu Univ.) |
(2)
VLD |
09:40-10:05 |
Use of the subgradient method to minimize half perimeter wirelength with consideration of cell overlap in analytical placement VLD2015-2 |
Hiroyuki Iwasaki, Hiroshi Miyashita (The Univ. of Kitakyushu) |
(3)
VLD |
10:05-10:30 |
NP-completeness of Routing Problem with Bend Constraint VLD2015-3 |
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech) |
| |
10:30-10:45 |
Break ( 15 min. ) |
Thu, May 14 AM
10:45 - 12:00 |
| (4) |
10:45-11:10 |
|
| (5) |
11:10-11:35 |
|
(6)
VLD |
11:35-12:00 |
Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits VLD2015-4 |
Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) |
| |
12:00-13:20 |
Lunch ( 80 min. ) |
Thu, May 14 PM
13:20 - 14:20 |
(7)
VLD |
13:20-14:20 |
[Invited Talk]
Trends and Future Challenges of Nano-electronics R&D in Japan VLD2015-5 |
Seiichiro Kawamura (JST) |
| |
14:20-14:35 |
Break ( 15 min. ) |
Thu, May 14 PM
14:35 - 15:50 |
| (8) |
14:35-15:00 |
|
(9)
VLD |
15:00-15:25 |
Power Analysis Method for a Lightweight Block Cipher Simon VLD2015-6 |
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
(10)
VLD |
15:25-15:50 |
AES Encryption Circuit against Clock Glitch based Fault Analysis VLD2015-7 |
Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Noriyuki Minegishi (Mitsubishi Electric Corporation)
E- :   gi       aj bielectc
Tel: 0467-41-2944 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
Makoto Sugihara (Kyushu University)
Email sldm2013 caitkshu-u |
| Announcement |
Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/ |
Last modified: 2015-04-24 16:01:43
|