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| Chair |
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Yuichi Hayashi (NAIST) |
| Vice Chair |
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Toru Akishita (Sony Semiconductor Solutions), Noriyuki Miura (Osaka Univ.) |
| Secretary |
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Toshihiro Sato (hd Lab,), Junichi Sakamoto (AIST) |
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| Chair |
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Makoto Ikeda (Univ. of Tokyo) |
| Vice Chair |
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Hayato Wakabayashi (Sony Semiconductor Solutions) |
| Secretary |
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Yoshiaki Yoshihara (Kioxia), Jun Shiomi (Osaka Univ.) |
| Assistant |
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Ryo Shirai (Kyoto Univ.), Kyoya Takano (Tokyo Univ. of Sci.), Takeshi Kuboki (Kumamoto University) |
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| Conference Date |
Fri, Nov 1, 2024 11:10 - 18:00 |
| Topics |
Hardware Security, etc. |
| Conference Place |
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| Sponsors |
This conference is co-sponsored by Graduate School of Science and Technology, Hirosaki University and IEEE SSCS Japan Chapter and IEEE SSCS Kansai Chapter.
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| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on HWS, ICD. |
| Due for Registration |
Please proceed the payment of registration fee by 3 days before the workshop date. The meeting URL will be sent from one of the secretaries of the committee via e-mail, just before the workshop date. |
| Registration for Online |
If you will join the workshop/conference held in online/hybrid style, please make your registration here, for getting the meeting ID and pass code. (Japanese page) |
| (1) |
11:10-11:15 |
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Fri, Nov 1 AM
11:15 - 12:30 |
| (2) |
11:15-11:40 |
Calculation of Target Reduction of Power Side-Channel Leakage for Hardware Design Based on Simulation |
Rei Mitsuyasu, Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) |
| (3) |
11:40-12:05 |
Fundamental Study on Frequency Injection Attack on True Random Number Generator Using Phase-Locked Loop |
Hikaru Nishiyama (AIST), Daisuke Fujimoto, Yuichi Hayashi (NAIST), Shinichi Kawamura (AIST) |
| (4) |
12:05-12:30 |
Examination of current status and issues for establishing minimum security requirements of semiconductor chips in embedded devices. |
Shinji Sato, Hirotaka Yoshida, Junichi Sakamoto, Kota Ideguchi (AIST), Makoto Nagata (Kobe Univ.), Shinichi Kawamura (AIST) |
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12:30-13:50 |
Break ( 80 min. ) |
Fri, Nov 1 PM
13:50 - 15:05 |
| (5) |
13:50-14:15 |
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| (6) |
14:15-14:40 |
Extension for Complex Movements of Human Detection System Using Broadcast Waves |
Risa Yashiro, Shinya Marubashi (SECOM), Taiki Kitazawa, Yuichi Hayashi (NAIST), Hiroki Kunii (SECOM) |
| (7) |
14:40-15:05 |
A study on authenticity determination using the electromagnetic characteristics of electronic devices |
Tsuyoshi Kobayashi, Yoshiki Kato, Takahiro Horiguchi, Mio Akahori (Mitsubishi Electric) |
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15:05-15:15 |
Break ( 10 min. ) |
Fri, Nov 1 PM
15:15 - 16:30 |
| (8) |
15:15-15:40 |
A Study on the Effectiveness of 1bit-fault Model in Statistical Fault Analysis |
Shungo Hayashi (AIST/YNU), Junichi Sakamoto, Hikaru Nishiyama, Tsutomu Matsumoto (AIST) |
| (9) |
15:40-16:05 |
Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips |
Yusuke Hayashi, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) |
| (10) |
16:05-16:30 |
Evaluation of Chip Internal Voltage Fluctuation and Digital Circuit Faults Induced by Electromagnetic Fault Injection Attacks |
Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.) |
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16:30-16:40 |
Break ( 10 min. ) |
Fri, Nov 1 PM
16:40 - 18:00 |
| (11) |
16:40-17:05 |
Integrated Multimodal Physical Attack Sensors for Lightweight Partial Re-Keying in Shared Group Key System |
Ryuki Ikemoto, Soichiro Fujii, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh (Osaka Univ.), Yuki Yamashita, Misato Taguchi, Takuji Miki, Makoto Nagata (Kobe Univ.), Yuichi Komano (CIT), Mitsugu Iwamoto, Kazuo Sakiyama (UEC), Noriyuki Miura (Osaka Univ.) |
| (12) |
17:05-17:30 |
Fixed Modulus Modular Reduction with Manipulated Lookup Table Method |
Anawin Opasatian, Makoto Ikeda (Tokyo Univ.) |
| (13) |
17:30-17:55 |
Secret Sharing Supporting Multi-input gates on FPGA Design for Less Communication Bandwidth Network |
Yinfan Zhao, Makoto Ikeda (UTokyo) |
| (14) |
17:55-18:00 |
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| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| HWS |
Technical Committee on Hardware Security (HWS) [Latest Schedule]
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| Contact Address |
Junichi Sakamoto (AIST), Toshihiro Sato (hd Lab, Inc.)
E- :hws- c  |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
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| Contact Address |
Yoshiaki Yoshihara (Kioxia Corporation)
E-:   a    oxia |
Last modified: 2024-09-20 14:32:11
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