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Technical Committee on Computer Systems (CPSY) (Searched in: 2017)
Search Results: Keywords 'from:2018-01-18 to:2018-01-18'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 09:15 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Yugo Yamauchi, Kazusa Musha (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.)  VLD2017-62 CPSY2017-106 RECONF2017-50 |
(To be available after the conference date) [more] | VLD2017-62 CPSY2017-106 RECONF2017-50 pp.1-6 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | All Binarized Conventional Neural Network and its Implementation on an FPGA
-- FPT2017 Design Competition Report -- Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) VLD2017-63 CPSY2017-107 RECONF2017-51 |
[more] | VLD2017-63 CPSY2017-107 RECONF2017-51 pp.7-11 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 10:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech) VLD2017-64 CPSY2017-108 RECONF2017-52 |
[more] | VLD2017-64 CPSY2017-108 RECONF2017-52 pp.13-18 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 10:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Kazutaka Ogihara (Fujitsu Lab.) VLD2017-65 CPSY2017-109 RECONF2017-53 |
(To be available after the conference date) [more] | VLD2017-65 CPSY2017-109 RECONF2017-53 pp.19-24 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 11:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2017-66 CPSY2017-110 RECONF2017-54 |
(To be available after the conference date) [more] | VLD2017-66 CPSY2017-110 RECONF2017-54 pp.25-29 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 11:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | VLD2017-67 CPSY2017-111 RECONF2017-55 |
(To be available after the conference date) [more] | VLD2017-67 CPSY2017-111 RECONF2017-55 pp.31-36 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 13:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) VLD2017-68 CPSY2017-112 RECONF2017-56 |
[more] | VLD2017-68 CPSY2017-112 RECONF2017-56 pp.37-42 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 13:25 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2017-69 CPSY2017-113 RECONF2017-57 |
[more] | VLD2017-69 CPSY2017-113 RECONF2017-57 pp.43-48 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 13:50 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Examination of the Normally-off using the stack circuit Kenji Sakamura (OPUGS), Kazutami Arimoto, Isao Kayano, Tomoyuki Yokogawa (OPU) VLD2017-70 CPSY2017-114 RECONF2017-58 |
In the stack circuit using charge recycling, low consumption electricity such as the streaming processing movement is ef... [more] | VLD2017-70 CPSY2017-114 RECONF2017-58 pp.49-51 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 14:25 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | VLD2017-71 CPSY2017-115 RECONF2017-59 |
Interconnection networks are key components for parallel and distributed computing systems, and they often become limiti... [more] | VLD2017-71 CPSY2017-115 RECONF2017-59 pp.53-58 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 15:35 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | VLD2017-72 CPSY2017-116 RECONF2017-60 |
(To be available after the conference date) [more] | VLD2017-72 CPSY2017-116 RECONF2017-60 pp.59-63 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 16:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Integrated Machine Code Monitor on FPGA Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) VLD2017-73 CPSY2017-117 RECONF2017-61 |
Machine code monitor is necessary for initial program development stage when implementing a new processor with unique IS... [more] | VLD2017-73 CPSY2017-117 RECONF2017-61 pp.65-70 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 16:35 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Daichi Tanaka, Antoniette Mondigo, Kentaro Sano, Satoru Yamamoto (Tohoku Univ) VLD2017-74 CPSY2017-118 RECONF2017-62 |
(To be available after the conference date) [more] | VLD2017-74 CPSY2017-118 RECONF2017-62 pp.71-76 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 17:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63 |
This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang prog... [more] |
VLD2017-75 CPSY2017-119 RECONF2017-63 pp.77-82 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 09:15 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT) VLD2017-76 CPSY2017-120 RECONF2017-64 |
[more] | VLD2017-76 CPSY2017-120 RECONF2017-64 pp.83-88 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2017-77 CPSY2017-121 RECONF2017-65 |
We expect reduce CPU resource consumptions by offloading processing stream data, which are incessantly generated such a... [more] |
VLD2017-77 CPSY2017-121 RECONF2017-65 pp.89-94 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 10:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Automatic Conversion from Snort PCRE to Verilog HDL Masahiro Fukuda, Yasushi Inoguchi (JAIST) VLD2017-78 CPSY2017-122 RECONF2017-66 |
In this paper, we present how to automatically convert Snort's PCRE (Perl Compatible Regular Expressions) into Verilog H... [more] | VLD2017-78 CPSY2017-122 RECONF2017-66 pp.95-100 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 10:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-79 CPSY2017-123 RECONF2017-67 |
This paper describes the design and implementation of a real-time optical flow processor using a single field-programmab... [more] | VLD2017-79 CPSY2017-123 RECONF2017-67 pp.101-106 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 11:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68 |
This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] | VLD2017-80 CPSY2017-124 RECONF2017-68 pp.107-112 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 11:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Total-ionizing-dose tolerance of an optically reconfigurable gate array Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) VLD2017-81 CPSY2017-125 RECONF2017-69 |
[more] | VLD2017-81 CPSY2017-125 RECONF2017-69 pp.113-117 |
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