IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

Technical Committee on Dependable Computing (DC)  (Searched in: 2013)

Search Results: Keywords 'from:2013-06-21 to:2013-06-21'
[Go to Official DC Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2013-06-21
13:45		 Tokyo Kikai-Shinko-Kaikan Bldg. A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10		 In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] DC2013-10
pp.1-6
DC 2013-06-21
14:15		 Tokyo Kikai-Shinko-Kaikan Bldg. A method of deterministic LFSR seed generation for scan-based BIST
Takanori Moriyasu, Satoshi Ohtake (Oita Univ.) DC2013-11		 This paper proposes a method of LFSR seed generation for LFSR reseeding of scan-based BIST of VLSI circuits. So far, a s... [more] DC2013-11
pp.7-12
DC 2013-06-21
14:45		 Tokyo Kikai-Shinko-Kaikan Bldg. A theretical discussion for testabilty of a degraded LSI in field
Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-12		 Various electronic systems that consist of variety of LSIs require very high reliability in field. However, physical deg... [more] DC2013-12
pp.13-18
DC 2013-06-21
15:30		 Tokyo Kikai-Shinko-Kaikan Bldg. An Approach of Generating a Test Set to Locate a Pair-Wise Interaction Fault
Takahiro Nagamoto, Hideharu Kojima, Tatsuhiro Tsuchiya (Osaka Univ.) DC2013-13		 This paper discusses the location of interaction faults in software interaction testing. Speci cally, we
propose a meth... [more]		 DC2013-13
pp.19-23
DC 2013-06-21
16:00		 Tokyo Kikai-Shinko-Kaikan Bldg. An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core
Kentaroh Katoh (TNCT) DC2013-14		 This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The pr... [more] DC2013-14
pp.25-29
DC 2013-06-21
16:30		 Tokyo Kikai-Shinko-Kaikan Bldg. A Method of Transistor Degradation Estimation Using Ring Oscillators
Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.) DC2013-15		 Aging called Negative Bias Temperature Instability (NBTI), Negative Bias Temperature Instability (NBTI) and Chanel Hot C... [more] DC2013-15
pp.31-36
 Results 1 - 6 of 6  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan