Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2016-02-17 10:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Note on Simultaneous Multiple Transient Fault Detection Based on Dual Approximate Logic Keisuke Sonehara, Masayuki Arai (Nihon Univ.) DC2015-86 |
[more] |
DC2015-86 pp.1-6 |
DC |
2016-02-17 10:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) DC2015-87 |
Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. Thi... [more] |
DC2015-87 pp.7-12 |
DC |
2016-02-17 10:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-88 |
As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic v... [more] |
DC2015-88 pp.13-18 |
DC |
2016-02-17 11:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) DC2015-89 |
Stochastic computing, which is a computational scheme with probabilities, is notable for its applicability to error tole... [more] |
DC2015-89 pp.19-24 |
DC |
2016-02-17 11:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Delay fault injection framework based on logic simulation with zero delay model Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-90 |
Fault injection is a technique to re-create faulty behavior of circuits and widely accepted method to evaluate soft erro... [more] |
DC2015-90 pp.25-30 |
DC |
2016-02-17 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Koji Yamazaki (Meiji Univ.) DC2015-91 |
[more] |
DC2015-91 pp.31-36 |
DC |
2016-02-17 14:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-92 |
Built-In Self-Test (BIST) is widely used to reduce test cost. However, it is difficult to achieve high fault coverage wi... [more] |
DC2015-92 pp.37-42 |
DC |
2016-02-17 14:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU) DC2015-93 |
Test point insertion methods to reduce the number of test patterns have been proposed for test cost reduction of VLSIs. ... [more] |
DC2015-93 pp.43-48 |
DC |
2016-02-17 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Analog Circuit Design for a Precision Resistance Measurement of TSVs Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-94 |
[more] |
DC2015-94 pp.49-54 |
DC |
2016-02-17 15:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
The Hybrid Communication Protocol for CANs Koji Konomi, Muneyuki Nakamura, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) DC2015-95 |
In controller area networks (CANs) on modern electronic vehicles and hybrid vehicles, noise level caused by high voltage... [more] |
DC2015-95 pp.55-59 |
DC |
2016-02-17 16:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Study on the Effect of Power Supply Noise on Flip-Flop Circuits Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2015-96 |
According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the o... [more] |
DC2015-96 pp.61-66 |