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Technical Committee on Dependable Computing (DC) (Searched in: 2008)
Search Results: Keywords 'from:2008-06-20 to:2008-06-20'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2008-06-20 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg | P2P Online Game Using Coterie Shuta Asano, Hiromi Kobayashi (Tokai Univ.)  DC2008-11 |
This paper presents a method of distributed online game using peer to peer (P2P) technology. Each peer performs a part o... [more] | DC2008-11 pp.1-6 |
| DC | 2008-06-20 13:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Online Game Protocol for P2P Using Byzantine Agreement Daisuke Wada, Hiromi Kobayashi (Tokai Univ.) DC2008-12 |
This paper presents an online game protocol to prevent dishonest activity called time-cheat for peer to peer (P2P) netwo... [more] | DC2008-12 pp.7-12 |
| DC | 2008-06-20 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Design of Highly Dependable Processor with the Tolerance to Multiple Simultaneous Transient Faults Makoto Kimura, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metroplitan Univ.) DC2008-13 |
We propose the methodology to make a highly reliable processor against multiple simultaneous transient faults. In our pr... [more] | DC2008-13 pp.13-18 |
| DC | 2008-06-20 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Test generation for multi-operand adders consisting of full adders Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) DC2008-14 |
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for it. Carry ... [more] | DC2008-14 pp.19-22 |
| DC | 2008-06-20 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Invited Talk]
The State of the Art and Future Trends of Test Design Yasuo Sato (Hitachi) DC2008-15 |
As the manufacturing process evolves with shrinking geometry and the speed of an LSI circuit increases, LSI testing tech... [more] | DC2008-15 pp.23-28 |
| DC | 2008-06-20 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Improving the Diagnostic Quality of Open Faults Koji Yamazaki, Toshiyuki Tsutsumi (Meiji Univ.), Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo (Ehime Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yuzo Takamatsu (Ehime Univ.) DC2008-16 |
With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and ... [more] | DC2008-16 pp.29-34 |
| DC | 2008-06-20 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Transistor Aging and Operational Environment of Logic Circuits Masafumi Haraguchi (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.) DC2008-17 |
With the progress of integrated circuit technology, it is becoming important to consider circuit aging. In this work we ... [more] | DC2008-17 pp.35-40 |
| DC | 2008-06-20 16:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Note on Hardware Overhead and Fault Location for Memory BIST Masayuki Arai, Kentaro Osawa, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao (Renesas) DC2008-18 |
[more] | DC2008-18 pp.41-46 |
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