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Technical Committee on Dependable Computing (DC) (Searched in: 2009)
Search Results: Keywords 'from:2009-04-21 to:2009-04-21'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY | 2009-04-21 11:00 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults Hideo Kohinata, Kohei Marumoto, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)  CPSY2009-1 DC2009-1 |
This paper proposes a novel technique to improve the reliability of sequential circuits. The proposed technique adopts t... [more] | CPSY2009-1 DC2009-1 pp.1-6 |
| DC, CPSY | 2009-04-21 11:25 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | A Development Process with A Model Checking Criterion Michitaka Inui (Mitsubishi Electric Micro-Computer Application Software Corp.), Nobukazu Yoshioka (NII) CPSY2009-2 DC2009-2 |
We have proposed a process for solving problems that we have to apply the model checking in a company. Also we have prop... [more] | CPSY2009-2 DC2009-2 pp.7-12 |
| DC, CPSY | 2009-04-21 13:00 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Evaluation of a Metropolis Algorithm for Constructing Unstructured Overlay Networks Tatsushi Takamura, Tatsuhiro Tsuchiya, Tohru Kikuno (Osaka Univ.) CPSY2009-3 DC2009-3 |
Peer-to-peer(P2P) systems use a virtual network called an overlay network to route messages to distinations. Some algor... [more] |
CPSY2009-3 DC2009-3 pp.13-17 |
| DC, CPSY | 2009-04-21 13:25 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | A Security Data-Flow Analysis in the Secure Software Development Environment DFITS Fukutomo Nakanishi, Ryotaro Hayashi, Hiroyoshi Haruki, Yurie Fujimatsu, Mikio Hashimoto (Toshiba Corp.) CPSY2009-4 DC2009-4 |
We proposed a development environment DFITS, which helps security programmers to create software against tampering in-me... [more] | CPSY2009-4 DC2009-4 pp.19-24 |
| DC, CPSY | 2009-04-21 13:50 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) CPSY2009-5 DC2009-5 |
This paper describes soft errors which are errors in LSI that are due to external radiation.The soft error rate (SER) wh... [more] | CPSY2009-5 DC2009-5 pp.25-30 |
| DC, CPSY | 2009-04-21 14:30 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | [Invited Talk]
Evolution and threat of botnet Toshiaki Sudou (NTT Communications) CPSY2009-6 DC2009-6 |
The damage of a variety of security problems such as Information leakage ,DDoS, and spam from terminal that hooks up to ... [more] | CPSY2009-6 DC2009-6 pp.31-35 |
| DC, CPSY | 2009-04-21 15:45 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | A design of testable response analyzers in built-in self-test Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2009-7 DC2009-7 |
In the BIST(Built-in self-test) scheme, the occurrence of faults in BIST circuits, e.g., test generators and response co... [more] | CPSY2009-7 DC2009-7 pp.37-42 |
| DC, CPSY | 2009-04-21 16:10 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design. Daisuke Kozuwa, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) CPSY2009-8 DC2009-8 |
The charge deposition that results from a neutron strikes to a transistor alter the memory state or the logic state of o... [more] | CPSY2009-8 DC2009-8 pp.43-48 |
| DC, CPSY | 2009-04-21 16:35 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Pulse Propagation Analysis for SER Evaluation of Logic Circuits Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ) CPSY2009-9 DC2009-9 |
As a transistor feature size scales down in recent years, soft error tends to increase. In logic circuits, a pulse genar... [more] | CPSY2009-9 DC2009-9 pp.49-54 |
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