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Technical Committee on Dependable Computing (DC) (Searched in: 2009)
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Search Results: Keywords 'from:2009-06-19 to:2009-06-19'
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[Go to Official DC Homepage (Japanese)] |
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Ascending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2009-06-19 10:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design method of easily testable parallel prefix adders Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ) DC2009-10 |
We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation... [more] |
DC2009-10 pp.1-6 |
DC |
2009-06-19 10:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Note on Yield and Area Trade-offs for MBIST in SoC Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao, Iwao Suzuki (Renesas Tech Corp.) DC2009-11 |
In this study we evaluate the effectiveness of hardware overhead reduction of memory BIST and spare assignment algorithm... [more] |
DC2009-11 pp.7-12 |
DC |
2009-06-19 11:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2009-12 |
If the existence of a fault in a circuit only causes negligible effect on its application,
the fault is said to be acce... [more] |
DC2009-12 pp.13-18 |
DC |
2009-06-19 11:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Diagnositc Test Generation for Transition Faults Using a Stuck-at ATPG Tool Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi (Ehime Univ.), Yoshihiro Simizu, Takashi Aikyo (STARC), Yuzo Takamatsu (Ehime Univ.) DC2009-13 |
In modern high-speed LSIs, defects that cause timing failure occur often, and thus their detection and diagnosis are get... [more] |
DC2009-13 pp.19-24 |
DC |
2009-06-19 13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
High-level Design for Test Tools & Industrial Design Flows Chouki Aktouf (DeFacTo) DC2009-14 |
Design for Testability at Register Transfer Level has been widely explored by academia. Commercial tools start
to be co... [more] |
DC2009-14 pp.25-28 |
DC |
2009-06-19 14:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Power & Noise Aware Test Utilizing Preliminary Estimation Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo (STARC) DC2009-15 |
Advances in low power design technologies is making issues on power dissipation and IR-drop in testing more serious. Exc... [more] |
DC2009-15 pp.29-30 |
DC |
2009-06-19 15:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
* Koichiro Noguchi, Koichi Nose (NEC Corp.), Toshinobu Ono (NEC Electronics Corp.), Masayuki Mizuno (NEC Corp.) DC2009-16 |
[more] |
DC2009-16 pp.31-34 |
DC |
2009-06-19 15:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Case study: Fault diagnosis for detecting systematic fault Hiroshi Yamamoto, Hiroki Wada, Toru Ogushi, Michinobu Nakao (Renesas Tech. Corp.) DC2009-17 |
Fault diagnosis for products is important for yield learning of the deep sub-micron technology due to various failure mo... [more] |
DC2009-17 p.35 |
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