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Technical Committee on Silicon Device and Materials (SDM) (Searched in: 2007)
Search Results: Keywords 'from:2008-03-14 to:2008-03-14'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2008-03-14 13:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | 15nm Planar Bulk SONOS-type Memory with Double Junstion Tunnel Layers Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba)  SDM2007-273 |
15nm gate length bulk-planar SONOS-type memory device, which has Si nanocrystal layer lying between double tunnel oxides... [more] | SDM2007-273 pp.1-6 |
| SDM | 2008-03-14 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Phase change memory with good data retention Takahiro Morikawa (CRL, Hitachi) |
[more] | |
| SDM | 2008-03-14 13:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fabrication and characterization of oxide-channel ferroelectric-gate nonvolatile memory devices Hiroshi Shibata, Tomohiro Oiwa, Eisuke Tokumitsu (Tokyo Tech) SDM2007-274 |
[more] | SDM2007-274 pp.7-12 |
| SDM | 2008-03-14 14:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Characteristics of metal-ferroelectric-insulartor-semiconductor structures based on poly(vinylidene fluoride-trifluoroethylene) Joo Won Yoon, Shun-ichiro Ohmi, Hiroshi Ishiwara (Tokyo Inst. of Tech) SDM2007-275 |
[more] | SDM2007-275 pp.13-16 |
| SDM | 2008-03-14 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Compliant Micro-Bumps for 3D Stacked-Chip LSIs with High Density Interconnection Implemented at Low Temperature Naoya Watanabe (Kumamoto TIF), Yutaka Iwasaki, Tanemasa Asano (Kyushu Univ.) SDM2007-276 |
We have proposed the compliant bump. The compliant bump, which can be made in the shape of pyramid or cone, has the pote... [more] | SDM2007-276 pp.17-20 |
| SDM | 2008-03-14 15:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding Naotaka Tanaka, Yasuhiro Yoshimura, Michihiro Kawashita (Hitachi), Toshihide Uematsu, Takahiro Naitoh, Takashi Akazawa (Renesas) SDM2007-277 |
One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are pot... [more] | SDM2007-277 pp.21-26 |
| SDM | 2008-03-14 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Realistic future trend of advanced non-volatile memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory Shigeyoshi Watanabe (SIT) SDM2007-278 |
[more] | SDM2007-278 pp.27-32 |
| SDM | 2008-03-14 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | New design technology of independent-gate controlled Double-Gate transistor for LSI Yu Hiroshima, Keisuke Okamoto, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2007-279 |
[more] | SDM2007-279 pp.33-38 |
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