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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2012)
Search Results: Keywords 'from:2013-03-04 to:2013-03-04'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2013-03-04 13:50 |
Okinawa | Okinawa Seinen Kaikan | A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  VLD2012-136 |
In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more] | VLD2012-136 pp.1-6 |
| VLD | 2013-03-04 14:15 |
Okinawa | Okinawa Seinen Kaikan | Acceleration of current-threshold determination toward on-line IDDQ testing through parameter estimation Michihiro Shintani, Takashi Sato (Kyoto Univ.) VLD2012-137 |
[more] | VLD2012-137 pp.7-12 |
| VLD | 2013-03-04 14:40 |
Okinawa | Okinawa Seinen Kaikan | Self-Compensation of Manufacturing Variability using On-Chip Sensors Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2012-138 |
Manufacturing variability is becoming more influential on circuit performance and parametric yield, and is predicted to ... [more] | VLD2012-138 pp.13-17 |
| VLD | 2013-03-04 15:20 |
Okinawa | Okinawa Seinen Kaikan | APR-based Legalization Method Shota Hirae, Maho Ishikawa, Yasuhiro Takashima (Univ. of Kitakyusyu) VLD2012-139 |
[more] | VLD2012-139 pp.19-24 |
| VLD | 2013-03-04 15:45 |
Okinawa | Okinawa Seinen Kaikan | TSV-aware Analytical Placement Koji Morita, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-140 |
In this paper, we propose a TSV-aware anlytical placement. Recently, to implement much large-scale LSI, a multi-layer LS... [more] | VLD2012-140 pp.25-29 |
| VLD | 2013-03-04 16:10 |
Okinawa | Okinawa Seinen Kaikan | Analytical Placement for Rectilinear Blocks Tomoaki Gotanda, Yasuhiro Takashima (Univ. of Kitakyusyu) VLD2012-141 |
[more] | VLD2012-141 pp.31-36 |
| VLD | 2013-03-04 16:35 |
Okinawa | Okinawa Seinen Kaikan | The minimum perturbation placement realization for convex blocks Hiroki Matsugano, Shota Hirae, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-142 |
In this paper, we propose the minimum perturbation placement realizetion for the convex blocks. The method is enhanced m... [more] | VLD2012-142 pp.37-42 |
| VLD | 2013-03-05 10:00 |
Okinawa | Okinawa Seinen Kaikan | An Automatic Nested Loop Pipelining method from C level behavior description Masahiro Nambu, Takashi Kambe (Kinki Univ.) VLD2012-143 |
Nested loop pipelining with keeping deta dependency is a key transformation in high-level synthesis tools as it helps ma... [more] | VLD2012-143 pp.43-48 |
| VLD | 2013-03-05 10:25 |
Okinawa | Okinawa Seinen Kaikan | An Acceleration method and its evaluation for Coarse Grained Reconfigurable Circuit Synthesis Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2012-144 |
High level synthesis for Coarse-grained architecture Reconfigurable Computing(CGA-RC) from high-level description is urg... [more] | VLD2012-144 pp.49-54 |
| VLD | 2013-03-05 10:50 |
Okinawa | Okinawa Seinen Kaikan | High Level Resynthesis Approach of Reusable RTL Property Msaato Tatsuoka, Mineo Kaneko (JAIST) VLD2012-145 |
Similar to RTL language that has been used as a design entry for LSI, a high-level description language such as SystemC,... [more] | VLD2012-145 pp.55-60 |
| VLD | 2013-03-05 11:15 |
Okinawa | Okinawa Seinen Kaikan | A Multi-Task Scheduling and Allocation for Highly Reliable Network-on-Chip Hiroshi Saito (Univ. of Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) VLD2012-146 |
[more] | VLD2012-146 pp.61-66 |
| VLD | 2013-03-05 13:00 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
Cyber-Physical Systems and LSI Design Technologies Shinpei Kato, Masato Edahiro (Nagoya Univ.) VLD2012-147 |
Our society faces a core challenge to societal problems, including environmental pollution and aging population , and in... [more] | VLD2012-147 pp.67-69 |
| VLD | 2013-03-05 14:05 |
Okinawa | Okinawa Seinen Kaikan | An Optimal Design Method for Input Signals of Small SoG-LCDs and Its Evaluation Taichi Suizu, Shuji Tsukiyama (Chuo Univ.) VLD2012-148 |
The driver circuit of a small Liquid Crystal Display (LCD) is formed on the same glass substrate as LCD by means of the ... [more] | VLD2012-148 pp.71-76 |
| VLD | 2013-03-05 14:30 |
Okinawa | Okinawa Seinen Kaikan | A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing Kyosuke Shinoda, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2012-149 |
In recent Printed Circuit Board (PCB) design, due to the growth of the density and the increase of the design scale the ... [more] | VLD2012-149 pp.77-82 |
| VLD | 2013-03-05 14:55 |
Okinawa | Okinawa Seinen Kaikan | A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2012-150 |
Parallel routing methods using various parallel computing environments have been proposed in existing studies for reduci... [more] | VLD2012-150 pp.83-88 |
| VLD | 2013-03-05 15:35 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) VLD2012-151 |
This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of... [more] |
VLD2012-151 p.89 |
| VLD | 2013-03-05 16:00 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation Michihiro Shintani, Takashi Sato (Kyoto Univ.) VLD2012-152 |
[more] | VLD2012-152 p.91 |
| VLD | 2013-03-05 16:25 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis Cong Hao, Song Chen, Takeshi Yoshimura (Waseda Univ.) VLD2012-153 |
In this work, we focus on the problem of latencyconstrained scheduling with consideration of multiple voltage technolo... [more] |
VLD2012-153 pp.93-98 |
| VLD | 2013-03-06 10:30 |
Okinawa | Okinawa Seinen Kaikan | A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling Takehiko Amaki, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Takao Onoye (Osaka Univ.) VLD2012-154 |
This paper presents a worst-case-aware design methodology for an oscillator-based true random number generator (TRNG) ro... [more] | VLD2012-154 pp.99-104 |
| VLD | 2013-03-06 10:55 |
Okinawa | Okinawa Seinen Kaikan | Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) VLD2012-155 |
In order to perform more efficient Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, it i... [more] | VLD2012-155 pp.105-110 |
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