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 Results 21 - 28 of 28 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2009-02-16
10:50
Tokyo   On the Acceleration of Redundancy Identification for Hard-to-ATPG faults Using SAT
Yusuke Akiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2008-70
Recently, 100% Fault coverage required in VLSI testing. However, ATPG algorithms can not classify all hard-to-test fault... [more] DC2008-70
pp.13-18
DC 2009-02-16
14:15
Tokyo   On Tests to Detect Open faults with Considering Adjacent Lines
Tetsuya Watanabe, Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ, Tokushima), Yuzo Takamatsu (Ehime Univ.) DC2008-74
In modern manufacturing technologies with the shrinking of manufacturing process, LSIs may have several metal interconne... [more] DC2008-74
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
14:15
Fukuoka Kitakyushu Science and Research Park Analysis of Open Fault using TEG Chip
Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) VLD2008-63 DC2008-31
The high integration of the semiconductor technology advances, and the fault detection and the failure diagnosis of LSI ... [more] VLD2008-63 DC2008-31
pp.19-24
DC 2008-06-20
15:50
Tokyo Kikai-Shinko-Kaikan Bldg Improving the Diagnostic Quality of Open Faults
Koji Yamazaki, Toshiyuki Tsutsumi (Meiji Univ.), Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo (Ehime Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yuzo Takamatsu (Ehime Univ.) DC2008-16
With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and ... [more] DC2008-16
pp.29-34
DC 2008-02-08
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. Fault Diagnosis for Dyinamic Open Faults with Considering Adjacent Lines
Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Syuhei Kadoyama, Tetsuya Watanabe, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Kouji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2007-68
In modern manufacturing technologies with the shrinking of manufacturing process, LSIs may have several metal interconne... [more] DC2007-68
pp.7-12
DC 2008-02-08
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Test Generation Method for Full Scan Circuit Using Multi Cycle Capture Test
Yusho Omori, Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Koji Yamazaki (Meiji Univ.) DC2007-70
Currently, scan testing is one of the most popular test methods for VLSIs. In this testing, only information of the circ... [more] DC2007-70
pp.19-24
DC 2008-02-08
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. A variable n-detection test generation method to increase fault sensitization coverage and evaluation of its test quality
Takeshi Tomita, Toshinori Hosokawa (Nihon University), Koji Yamazaki (Meiji University) DC2007-71
N-deteciton test generation is known as one of the generation method of high-quality test set. However, many tests which... [more] DC2007-71
pp.25-31
DC 2008-02-08
15:40
Tokyo Kikai-Shinko-Kaikan Bldg. Comparison of exact solutions and greedy solutions in static test compaction
Kei Yagisawa, Koji Yamazaki (Meiji Univ.), Toshinori Hosokawa (Nihon Univ.), Hisao Tamaki (Meiji Univ.) DC2007-79
In this paper, we formulate static test compaction using don't cares as a minimum clique cover problem and a vertex colo... [more] DC2007-79
pp.77-82
 Results 21 - 28 of 28 [Previous]  /   
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