| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Network Performance of Multifunction On-chip Router Architectures Shinya Takamaeda-Yamazaki, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.)  CPSY2012-52 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR (Dual Modular Redunda... [more] | CPSY2012-52 pp.27-32 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
Efficient Execution of Floating Point Instructions in CRIB Naoaki Ohkubo, Kenji Kise (TokyoTech) ICD2011-113 |
In recent high-performance processor, instruction scheduling, register renaming, and physical register file consume sign... [more] | ICD2011-113 p.67 |
|
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 16:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Validation of FPGA-based Many-core Simulator ScalableCore System Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech) VLD2010-112 CPSY2010-67 RECONF2010-81 |
We have proposed and been developing the ScalableCore system, FPGA-based simulation system for tile many-core architectu... [more] | VLD2010-112 CPSY2010-67 RECONF2010-81 pp.187-192 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 16:25 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA Naoki Fujieda, Kenji Kise (Tokyo Tech) VLD2010-113 CPSY2010-68 RECONF2010-82 |
To output results of, or to debug, embedded systems, display modules which is easy to connect and shows much information... [more] | VLD2010-113 CPSY2010-68 RECONF2010-82 pp.193-198 |
| RECONF | 2010-09-17 13:40 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Implementation and Evaluation of ScalableCore System 2.0 Yoshito Sakaguchi, Shinya Takamaeda, Kenji Kise (Tokyo Tech) RECONF2010-38 |
ScalableCore is a concept of prototyping system development by using a lot of FPGAs for Many-core architecture researche... [more] | RECONF2010-38 pp.121-126 |
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | Implementaton and evaluation of light weight high speed serial communications with Error Correcting Code Yoshito Sakaguchi, Mochamad Asri, Shinya Takamaeda, Haruhiko Kaneko, Kenji Kise (Tokyo Inst. of Tech.) CPSY2010-19 |
Errror correcting code is required, which is capable enough of correctiong errors, implementable with low resources and... [more] |
CPSY2010-19 pp.67-72 |
| CPSY | 2009-11-20 15:55 |
Kyoto | Campus Plaza Kyoto | A Study of Task Allocation Problem for Many-core Processor with Consideration of Network Traffic Shintaro Sano, Masahiro Sano, Shimpei Sato (Tokyo Inst. of Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech./JST), Kenji Kise (Tokyo Inst. of Tech.) CPSY2009-40 |
In many-core architecture that has dozens of cores in processor, it is important to improve performance by using paralle... [more] | CPSY2009-40 pp.31-36 |
| RECONF | 2009-09-18 10:25 |
Tochigi | Utsunomiya Univ. | A Study of Scalable Prototyping System with Small-sized FPGAs Shimpei Watanabe, Shinya Takamaeda, Ken Kyou (Tokyo Inst. of Tech), Takefumi Miyoshi (Tokyo Inst. of Tech/JST), Kenji Kise (Tokyo Inst. of Tech) RECONF2009-31 |
In order to practically simulate many-core processor, the authors proposed ScalableCore which is a hardware simulator. ... [more] |
RECONF2009-31 pp.73-78 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 16:00 |
Osaka | Shoushin Kaikan | The Cache-Core optimization on Multi-CoreProcessors considering several overheads Yosuke Mori, Akira Moriya, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) |
The number of cores in a processor increases. If several cores access to the main memory at the same time, the memory... [more] |
ICD2008-147 pp.105-110 |
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