IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

Technical Committee on Computer Systems (CPSY)  (Searched in: 2012)

Search Results: Keywords 'from:2012-11-26 to:2012-11-26'

[Go to Official CPSY Homepage] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 21 - 40 of 80 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
09:00
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] High-Speed Interconnect Technologies
Yutaka Uematsu, Go Shinkai, Satoshi Muraoka, Masayoshi Yagyu, Hideki Osaka (Hitachi) CPM2012-112 ICD2012-76
 [more] CPM2012-112 ICD2012-76
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
09:30
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] Passive Intermodulation Observed in linearly designed circuits
Nobuhiro Kuga, Daijiro Ishibashi (Yokohama National Univ.) CPM2012-113 ICD2012-77
 [more] CPM2012-113 ICD2012-77
pp.7-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
09:00
Fukuoka Centennial Hall Kyushu University School of Medicine A Method to Parallelize Simulated Annealing Algorithm by Generating Look-ahead Neighbor Solutions
Yusuke Ota, Kazuhito Ito (Saitama Univ.) VLD2012-73 DC2012-39
Simulated annealing (SA) is a general method to solve combinational optimization problems. SA generates a neigh¬bor solu... [more] VLD2012-73 DC2012-39
pp.81-86
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
09:25
Fukuoka Centennial Hall Kyushu University School of Medicine An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method
Yukihide Kohira (UoA), Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-74 DC2012-40
In this paper, we propose an acceleration method by GPGPU for an analytical placement method using a quasi-Newton method... [more] VLD2012-74 DC2012-40
pp.87-92
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
09:50
Fukuoka Centennial Hall Kyushu University School of Medicine An ILP Formulation of Placement and Routing for PLDs
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) VLD2012-75 DC2012-41
In this paper, we formulate the simultaneous technology mapping, placement and
routing problem for programmable gate a... [more]
VLD2012-75 DC2012-41
pp.93-98
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:30
Fukuoka Centennial Hall Kyushu University School of Medicine A study on Hardware Trojan embedded Manchurian and its detection approach for triple DES processing
Youhei Mochizuki, Takeshi Kumaki (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ) CPSY2012-53
 [more] CPSY2012-53
pp.33-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:55
Fukuoka Centennial Hall Kyushu University School of Medicine An FPGA Implementation of Reconfigurable Real-Time Vision Architecture
Jorge Hiraiwa, Hideharu Amano (Keio Univ.) CPSY2012-54
A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently,... [more] CPSY2012-54
pp.39-44
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:15
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] Expectations to 2.5D/3D Package and Challenges on Package Design
Hiroyuki Mori, Kazushige Toriyama, Yasumitsu Orii (IBM Japan) CPM2012-114 ICD2012-78
 [more] CPM2012-114 ICD2012-78
pp.11-14
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:45
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] Overview of 3D Integration Technology and Challenges for Volume Production
Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi (Tohoku Univ.) CPM2012-115 ICD2012-79
 [more] CPM2012-115 ICD2012-79
pp.15-22
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
11:15
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] Novel Packaging Design by Appling Metamaterial Structures
Takashi Harada, Hiroshi Toyao, Yoshiaki Kasahara (NEC Corp.) CPM2012-116 ICD2012-80
 [more] CPM2012-116 ICD2012-80
pp.23-28
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:30
Fukuoka Centennial Hall Kyushu University School of Medicine A speculative execution method for indefinite loops in high level synthesis
Tatsuma Araki, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ) VLD2012-76 DC2012-42
 [more] VLD2012-76 DC2012-42
pp.99-104
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:55
Fukuoka Centennial Hall Kyushu University School of Medicine A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation
Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) VLD2012-77 DC2012-43
In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementat... [more] VLD2012-77 DC2012-43
pp.105-110
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
11:20
Fukuoka Centennial Hall Kyushu University School of Medicine Controller Synthesis for Clock Improvement in Behavioral Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2012-78 DC2012-44
 [more] VLD2012-78 DC2012-44
pp.111-116
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
13:00
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] Application Examples of FPGA -- Parallel Computers and Network --
Yuetsu Kodama (Univ. of Tsukuba) RECONF2012-46
I introduce my previous and current research works using FPGA. First
is EM-X on REX, that is an emulator of original mu... [more]
RECONF2012-46
pp.1-2
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
13:50
Fukuoka Centennial Hall Kyushu University School of Medicine Low Power Reconfiguarable Accelerator Design with Silicon on Thin Buried Oxide
Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) RECONF2012-47
Nowadays,with the development of low power supply voltage Vdd,it is becoming a serious issue that the bios of threshold ... [more] RECONF2012-47
pp.3-8
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
14:15
Fukuoka Centennial Hall Kyushu University School of Medicine A study on reconfigurable direct conversion JAVA accelerator for embedded systems
Seiya Takada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2012-48
In embedded systems, the requirements for short-time and low-cost development have been increased
recently. For this re... [more]
RECONF2012-48
pp.9-14
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
13:00
Fukuoka Centennial Hall Kyushu University School of Medicine Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors
Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2012-79 DC2012-45
With the increased operating frequency and the reduction of feature
size, achieving low error-rate data transmission be... [more]
VLD2012-79 DC2012-45
pp.117-122
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
13:25
Fukuoka Centennial Hall Kyushu University School of Medicine Analytical model of energy dissipation for comparing adder architectures
Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) VLD2012-80 DC2012-46
This paper describes analytical models for delay and energy dissipation of ripple-carry, carry look-ahead, and parallel ... [more] VLD2012-80 DC2012-46
pp.123-128
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
13:50
Fukuoka Centennial Hall Kyushu University School of Medicine Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures
Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-81 DC2012-47
With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown s... [more] VLD2012-81 DC2012-47
pp.129-134
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
14:15
Fukuoka Centennial Hall Kyushu University School of Medicine SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-82 DC2012-48
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] VLD2012-82 DC2012-48
pp.135-140
 Results 21 - 40 of 80 [Previous]  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan