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Technical Committee on Reconfigurable Systems (RECONF)  (Searched in: 2012)

Search Results: Keywords 'from:2013-01-16 to:2013-01-16'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 21 - 29 of 29 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
11:00		 Kanagawa   Comparison between single host multi-GPU system with ExpEther and multi host system
Shimpei Nomura, Tetsuya Nakahama (Keio Univ.), Junichi Higuchi, Yuki Hayashi, Takashi Yoshikawa (NEC), Hideharu Amano (Keio Univ.) VLD2012-127 CPSY2012-76 RECONF2012-81		 Clusters with GPUs become widespread because they provide high peak performance and good perfor- mance per cost. However... [more] VLD2012-127 CPSY2012-76 RECONF2012-81
pp.117-122
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
11:25		 Kanagawa   Low latency network topology using multiple links at each host
Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) VLD2012-128 CPSY2012-77 RECONF2012-82		 End-to-end network latency has become an important issue for parallel application on large-scale High Performance Comput... [more] VLD2012-128 CPSY2012-77 RECONF2012-82
pp.123-128
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
13:00		 Kanagawa   A design of a line buffer module for image proccessing as a library of a high-level synthesis environment
Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.) VLD2012-129 CPSY2012-78 RECONF2012-83		  [more] VLD2012-129 CPSY2012-78 RECONF2012-83
pp.129-134
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
13:25		 Kanagawa   A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84		 Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] VLD2012-130 CPSY2012-79 RECONF2012-84
pp.135-140
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
13:50		 Kanagawa   The method for automation of design verification using UML diagram
Daiki Kano (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) VLD2012-131 CPSY2012-80 RECONF2012-85		 We develop the method for hardware design using UML diagram, in order to develop the hardware efficiently.We propose the... [more] VLD2012-131 CPSY2012-80 RECONF2012-85
pp.141-146
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
14:25		 Kanagawa   Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool
Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-132 CPSY2012-81 RECONF2012-86		 In this paper, we describe an implementation of a pupil detection using MaxCompiler which is a high-level synthesis fram... [more] VLD2012-132 CPSY2012-81 RECONF2012-86
pp.147-152
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
14:50		 Kanagawa   Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool
Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-133 CPSY2012-82 RECONF2012-87		 In this paper, we implemented a stencil computation kernel on an FPGA accelerator using MaxCompiler and MaxGenFD tools, ... [more] VLD2012-133 CPSY2012-82 RECONF2012-87
pp.153-158
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
15:15		 Kanagawa   Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) VLD2012-134 CPSY2012-83 RECONF2012-88		 We develop an effective stencil computation accelerator by using multiple FPGAs, which employs 2D-mesh architecture conn... [more] VLD2012-134 CPSY2012-83 RECONF2012-88
pp.159-164
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
15:40		 Kanagawa   Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster
Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) VLD2012-135 CPSY2012-84 RECONF2012-89		  [more] VLD2012-135 CPSY2012-84 RECONF2012-89
pp.165-170
 Results 21 - 29 of 29 [Previous]  /   
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