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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ED 2007-02-01
16:00		 Hokkaido   Investigation of A Novel Logic Circuit Implementation Scheme Utilizing Topological Correlation between Logic Graph by Decision Diagram and Nanowire Network Structures
Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori (Hokkaido Univ.) 		This report presents study on a novel scheme to implement logic information processing function on nanowire network stru... [more] ED2006-245 SDM2006-233
pp.29-34
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