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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 41 - 57 of 57 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
15:05		 Kanagawa Keio Univ (Hiyoshi Campus) Acceleration of Regression Test of Compilers by Program Merging
Kazushi Morimoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Yuki Uchiyama (K-OPT), Nobuyuki Hikichi (SRA, Inc) VLD2010-94 CPSY2010-49 RECONF2010-63		 This article presents a method of accelerating regression test of compilers by merging programs in test suites. Testing ... [more] VLD2010-94 CPSY2010-49 RECONF2010-63
pp.63-67
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
15:25		 Kanagawa Keio Univ (Hiyoshi Campus) Automatic Retargeting of Binutils and GDB Based on Plug-in Method
Soichiro Taga (Kwansei Gakuin Univ.), Takahiro Kumura (NEC/Osaka Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2010-95 CPSY2010-50 RECONF2010-64		 This paper proposes a method of automatic retargeting of software development tools based on a plug-in method. The plug-... [more] VLD2010-95 CPSY2010-50 RECONF2010-64
pp.69-74
VLD 2010-03-12
10:00		 Okinawa   Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
Takahiro Kumura (NEC/Osaka Univ.), Soichiro Taga, Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2009-120		 This paper proposes a method of software development tool generation suitable for instruction set extension of existing ... [more] VLD2009-120
pp.127-132
VLD 2009-03-11
10:30		 Okinawa   Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution
Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126		 This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] VLD2008-126
pp.1-6
VLD 2009-03-11
10:55		 Okinawa   Random Testing for Arithmetic Optimization of C compilers
Hironobu Awazu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2008-127		 This article presents random testing of C compilers focusing on arithmetic optimization. It tests if code generation and... [more] VLD2008-127
pp.7-10
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
16:10		 Kanagawa   Extension of High Level Synthesis system CCAP for AMP multi-core system desin
Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM) VLD2008-105 CPSY2008-67 RECONF2008-69		  [more] VLD2008-105 CPSY2008-67 RECONF2008-69
pp.81-86
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-19
10:00		 Fukuoka Kitakyushu Science and Research Park Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations
Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin Univ.) VLD2008-83 DC2008-51		 This article presents variable scheduling and binding for high-level synthesis.
Conventional scheduling algorithms deci... [more]		 VLD2008-83 DC2008-51
pp.139-144
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
16:50		 Kanagawa Hiyoshi Campus, Keio University VLIW Extension of Software Development Environment Construction Tool ArchC
Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2007-134 CPSY2007-77 RECONF2007-80		 ArchC is a C++/SystemC-based open-source software，which generates software development environments (consisting of Binut... [more] VLD2007-134 CPSY2007-77 RECONF2007-80
pp.95-100
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
14:55		 Fukuoka Kitakyushu International Conference Center Cycle Partitioned Scheduling for Code Optimization of VLIW DSP
Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2007-102 DC2007-57		 This paper proposes a cycle partitioned scheduling method for code optimization of VLIW DSPs. The previously proposed op... [more] VLD2007-102 DC2007-57
pp.79-84
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
15:20		 Fukuoka Kitakyushu International Conference Center Retargetable Linear Assembler for VLIW Processor
Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.) VLD2007-103 DC2007-58		 This paper proposes a retargetable linear assembler
as a software development tool for custom VLIW processors.
The ret... [more]		 VLD2007-103 DC2007-58
pp.85-90
VLD, IPSJ-SLDM 2007-05-10
16:00		 Kyoto Kyodai Kaikan [Panel Discussion] Highlevel synthesis; will it be useful or useless?
Masahiro Fukui (Ritsumeikan Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Tomonori Izumi (Ritsumeikan Univ.), Akihisa Yamada (SHARP) VLD2007-6		 As to utilizing high-level synthesis tools effectively, we plan to discuss from the views of LSI designers, high-level s... [more] VLD2007-6
p.31
VLD, CPSY, RECONF, IPSJ-SLDM 2007-01-18
09:45		 Tokyo Keio Univ. Hiyoshi Campus Optimum Code Scheduling for Clustered VLIW DSP Using Pseudo Boolean Satisfiability
Ryo Kobayashi, Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) 		 [more] VLD2006-94 CPSY2006-65 RECONF2006-65
pp.1-5
VLD, CPSY, RECONF, IPSJ-SLDM 2007-01-18
10:10		 Tokyo Keio Univ. Hiyoshi Campus Test Suite for C Compilers and Its Generating Tool testgen
Yuki Uchiyama (Kwansei Gakuin Univ.), Nobuyuki Hikichi (SRA), Nagisa Ishiura, Yuji Nagamatsu (Kwansei Gakuin Univ.) 		 [more] VLD2006-95 CPSY2006-66 RECONF2006-66
pp.7-11
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-18
13:50		 Kanagawa   Retargeting GCC and GNU Toolchain for Extended Instruction Set
Yuji Nagamatsu, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuyuki Hikichi (SRA-KTL) 		While ASIPs (Application Specific Instruction set Processors) are attractive components for embedded systems, constructi... [more] VLD2005-103 CPSY2005-59 RECONF2005-92
pp.37-41
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
11:00		 Fukuoka Kitakyushu International Conference Center Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP
Kenichi Nishiguchi, Nagisa Ishiura, Masanari Nishimura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Nagoya Univ.), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ.) 		We are developing a high-level synthesis tool named CCAP (C Compatible Architecture Prototyper), which synthesizes arbit... [more] VLD2005-79 ICD2005-174 DC2005-56
pp.19-24
CPSY, VLD, IPSJ-SLDM 2005-01-26
15:10		 Kanagawa   Extraction of Instruction Latency from Cycle-True Processor Models
Yusuke Hiraoka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ) 		 [more] VLD2004-119 CPSY2004-85
pp.55-60
CPSY, VLD, IPSJ-SLDM 2005-01-26
15:40		 Kanagawa   Instruction Pattern Generation for Retargetable Compiler
Atsushi Kishimoto, Nagisa Ishiura, Yuuki Masui (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.) 		 [more] VLD2004-120 CPSY2004-86
pp.61-66
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