Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] |
2024-07-22 17:05 |
Hokkaido |
Sapporo Convention Center |
Power-analysis side channel attack with auto encoder Haruto Ishii, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UTokyo) |
[more] |
|
NS, IN (Joint) |
2024-03-01 14:15 |
Okinawa |
Okinawa Convention Center |
Ransomware Detection using Traffic Features in SDN Ken Tanase, Kunio Akashi, Yuji Sekiya, Hiroshi Nakamura (Tokyo Univ.) NS2023-237 |
In recent years, ransomware has emerged as a significant threat to information security in organizations.
A particular... [more] |
NS2023-237 pp.385-390 |
VLD, HWS, ICD |
2024-02-29 09:20 |
Okinawa |
(Primary: On-site, Secondary: Online) |
A Scalable Mapping Method for Elastic CGRAs Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT) VLD2023-106 HWS2023-66 ICD2023-95 |
[more] |
VLD2023-106 HWS2023-66 ICD2023-95 pp.42-47 |
RECONF |
2023-09-14 16:50 |
Tokyo |
Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Construction of Visualization Environment for CGRA Operation Verification Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT) RECONF2023-25 |
[more] |
RECONF2023-25 pp.20-21 |
RECONF |
2023-06-08 15:10 |
Kochi |
Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
Study on mapping methods for Elastic CGRA Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT) RECONF2023-1 |
CGRA (Coarse-Grained Reconfigurable Architecture) is an architecture with a two-dimensional array of processing elements... [more] |
RECONF2023-1 pp.1-6 |
HWS, VLD |
2023-03-02 11:00 |
Okinawa |
(Primary: On-site, Secondary: Online) |
VLD2022-88 HWS2022-59 |
(To be available after the conference date) [more] |
VLD2022-88 HWS2022-59 pp.91-96 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-28 14:20 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
A Study of a Design Methodology for Various CGRA based on Diplomacy Takuya Kojima (UTokyo/JST PRESTO), Makoto Saito, Hiroshi Nakamura (UTokyo) VLD2022-22 ICD2022-39 DC2022-38 RECONF2022-45 |
(To be available after the conference date) [more] |
VLD2022-22 ICD2022-39 DC2022-38 RECONF2022-45 pp.19-24 |
RECONF |
2022-06-07 13:25 |
Ibaraki |
CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Shoin Maeda, Hiroshi Nakamura, Hideki Takase (UT) RECONF2022-2 |
To expand the application area of model predictive control (MPC), a control system design framework that guarantees the ... [more] |
RECONF2022-2 pp.7-12 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2022-03-11 14:50 |
Online |
Online |
GA-based Software Pipeline Scheduling for CGRAs Masato Nakagawa, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UTokyo) CPSY2021-65 DC2021-99 |
(To be available after the conference date) [more] |
CPSY2021-65 DC2021-99 pp.120-125 |
RCS |
2021-06-23 16:10 |
Online |
Online |
Proof of concept of Normally-off type local 5G base station Kazutami Arimoto (Okaya.a Prefectural Univ.), Hiroshi Nakamura, Ryuichi Sakamoto, Yuta Suzuki (Univ. of Tokyo), Hideharu Takebe (poco-apoco Networks), Noriaki Yoshikawa, Kensaku Kinosita (Cyber Creative Institute), Tomoyuki Ohya (DOCOMO Technology) RCS2021-44 |
Using open software and software defined radio, we developed a proof-of-concept facility (PoC) for a normally-off local ... [more] |
RCS2021-44 pp.91-96 |
IN, NS (Joint) |
2021-03-05 11:20 |
Online |
Online |
Proposal for LDoS attack using indirect transmission in Zigbee and a countermeasure against it Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura (The University of Tokyo) NS2020-153 |
Low-Rate DoS (LDoS) attack degrades the quality of service with less traffic than typical DoS attacks. LDoS attack has a... [more] |
NS2020-153 pp.179-184 |
CPSY, DC, IPSJ-ARC [detail] |
2020-07-30 16:15 |
Online |
Online |
Preliminary examination of normally-off power management for local 5G base station Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura (UTokyo) CPSY2020-5 DC2020-5 |
It is necessary to reduce power consumption of base stations (BSs) in local 5G network. This article proposes applying n... [more] |
CPSY2020-5 DC2020-5 pp.29-35 |
SR, NS, SeMI, RCC, RCS (Joint) |
2020-07-09 13:00 |
Online |
Online |
Concept of Normally-off type local 5G base station with energy matching AI Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Nakamura, Ryuichi Sakamoto, Yuta Suzuki (Univ. of Tokyo), Hideharu Takebe (poco-apoco Networks Co. Ltd), Noriaki Yoshikawa, Kensaku Kinosita (Cyber Creative Institute Co., Ltd.) RCC2020-4 NS2020-33 RCS2020-67 SR2020-12 SeMI2020-4 |
[more] |
RCC2020-4 NS2020-33 RCS2020-67 SR2020-12 SeMI2020-4 pp.13-18(RCC), pp.13-18(NS), pp.55-60(RCS), pp.19-24(SR), pp.7-12(SeMI) |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 13:00 |
Ehime |
Ehime Prefecture Gender Equality Center |
[Keynote Address]
Prospect for Knowledge Intensive Society leveraged by VLSI Design Hiroshi Nakamura (UTokyo) VLD2019-39 ICD2019-29 IE2019-35 CPSY2019-42 DC2019-63 RECONF2019-40 |
(To be available after the conference date) [more] |
VLD2019-39 ICD2019-29 IE2019-35 CPSY2019-42 DC2019-63 RECONF2019-40 p.95(VLD), p.5(ICD), p.5(IE), p.5(CPSY), p.95(DC), p.23(RECONF) |
ICD |
2018-04-20 11:10 |
Tokyo |
|
[Invited Talk]
A 512Gb 3b/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Toshifumi Hashimoto (TMC), Hao Nguyen, Ken Cheah, Hiroshi Sugawara, Seungpil Lee (WDC), Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura (TMC) ICD2018-10 |
A 512Gb 3b/cell flash has been developed on a 96-WL-layer BiCS FLASH technology. This work implements three key technolo... [more] |
ICD2018-10 pp.39-44 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2017-03-10 14:30 |
Okinawa |
Kumejima Island |
Compiler Toolchain of Deep Learning Accelerator with Wireless 3D Stacked Chips Tetsui Ohkubo, Takuya Kojima, Hideharu Amano (Keio Univ.), Ryo Takata, Jun Ishii, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura (Tokyo Univ.) CPSY2016-155 DC2016-101 |
[more] |
CPSY2016-155 DC2016-101 pp.357-362 |
ICD, MW |
2016-03-02 14:55 |
Hiroshima |
Hiroshima University |
[Invited Talk]
An implementation of a building block system with TCI (Thru-Chip Interface) using SOTB process Hideharu Amano (Keio Univ.), Masayoshi Usami (SIT), Tadahiro Kuroda (Keio Univ.), Masaaki Kondo (Univ. of Tokyo), Yasuhiro Take (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Mitaro Namiki (TUAT), Hiroki Matsutani (Keio Univ.) MW2015-182 ICD2015-105 |
[more] |
MW2015-182 ICD2015-105 pp.49-54 |
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] |
2015-03-07 09:20 |
Kagoshima |
|
A Study on a Power Efficient Neurochip with Non-Volatile Memory Jun Tomii, Masaaki Kondo, Hiroshi Nakamura (Univ. Tokyo) CPSY2014-176 DC2014-102 |
Along with the evolution of machine learning techniques, neurochips, which are designed for fast neural network processi... [more] |
CPSY2014-176 DC2014-102 pp.83-88 |
CPSY, DC (Joint) |
2014-07-30 15:15 |
Niigata |
Toki Messe, Niigata |
Spatiotemporal compression and hierarchization for low-power sensor networks Takashi Nakada, Yukito Tanaka (Univ. of Tokyo), Keiro Muro (Hitachi), Takeo Murakami, Shintaro Fujisaki (Hitachi Information & Telecommunication Engineering), Takanori Shimura, Taizo Kinoshita (Hitachi), Hiroshi Nakamura (Univ. of Tokyo) CPSY2014-40 |
Minimizing the energy consumption of sensor network systems is a very critical concern. As a result, we need to minimize... [more] |
CPSY2014-40 pp.179-184 |
CPSY, DC (Joint) |
2014-07-30 18:15 |
Niigata |
Toki Messe, Niigata |
Design of OpenCL Library and Execution Dispatcher for Embedded Accelerator Ryuichi Sakamoto, Mikiko Sato (Tokyo Univ. of Agriculture and Tech. (TUAT)), Hideharu Amano, Tadahiro Kuroda (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hiroshi Nakamura (Univ. of Tokyo), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech. (TUAT)) CPSY2014-46 |
Recently, an embedded processor for use in smartphones and other devices is equipped with some power-efficient accelerat... [more] |
CPSY2014-46 pp.215-220 |