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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 10 of 10  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
16:15
Fukuoka Kitakyushu Science and Research Park A Parallel Hardware Engine for Generating Deformed Maps
Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-67 DC2008-35
 [more] VLD2008-67 DC2008-35
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
13:00
Fukuoka Kitakyushu Science and Research Park Scan-based Attack for an AES-LSI included with other IPs
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2008-68 DC2008-36
The threat of side-channel attacks of cryptography LSIs is indicated.
Recently, Scan-based attacks using the scan chain... [more]
VLD2008-68 DC2008-36
pp.49-53
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
13:25
Fukuoka Kitakyushu Science and Research Park Dynamically Variable Secure Scan Architecture against Scan-based Side Channel Attack on Cryptography LSIs
Hiroshi Atobe, Ryuta Nara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-69 DC2008-37
Scan test is a powerful and popular test technique because it can control and observe the internal states of the circuit... [more] VLD2008-69 DC2008-37
pp.55-59
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
13:50
Fukuoka Kitakyushu Science and Research Park A Power Masking Method of AES Circuit By Using Cross Bar Switch To Switch S-Box Circuit.
Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2008-70 DC2008-38
 [more] VLD2008-70 DC2008-38
pp.61-66
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-21
16:35
Fukuoka Kitakyushu International Conference Center A power masking multiplying circuit based on galois field for composite field AES
Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-88 DC2007-43
 [more] VLD2007-88 DC2007-43
pp.37-42
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-22
14:30
Fukuoka Kitakyushu International Conference Center A Hardware Engine for Generation Deformed Map
Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-99 DC2007-54
 [more] VLD2007-99 DC2007-54
pp.61-66
CAS, SIP, VLD 2007-06-22
13:00
Hokkaido Hokkaido Tokai Univ. (Sapporo) Scalable Dual-Radix Unified Montgomery Multiplier in GF(p) and GF(2n)
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) CAS2007-26 VLD2007-42 SIP2007-56
Modular multiplication is the dominant arithmetic operation in elliptic curve cryptography (ECC), which is one of public... [more] CAS2007-26 VLD2007-42 SIP2007-56
pp.43-48
VLD, IPSJ-SLDM 2007-05-11
11:20
Kyoto Kyodai Kaikan An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem
Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-11
Originally elliptic curve cryptosystem (ECC) hardware are often required to operate variable key length. Digit-serial mu... [more] VLD2007-11
pp.25-29
VLD, CPSY, RECONF, IPSJ-SLDM 2007-01-17
15:15
Tokyo Keio Univ. Hiyoshi Campus GF(2^m) Digit-Serial Multiplier for Elliptic Curve Cryptosystem
Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Masao Yanagisawa, Satoshi Goto, Tatsuo Ohtsuki (Waseda Univ)
 [more] VLD2006-89 CPSY2006-60 RECONF2006-60
pp.25-30
VLD, ICD 2005-03-10
- 2005-03-11
Okinawa Mielparque Okinawa A Fast Elliptic Curve Cryptosystem LSI embedding Ward-Based Montgomery Multiplier
Jumpei Uchida, Ryuta Nara, Yuichiro Miyaoka (Waseda Univ.), Nozomu Togawa (The Univ. of Kitakyushu), Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
 [more] VLD2004-125 ICD2004-221
pp.5-10
 Results 1 - 10 of 10  /   
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