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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EID, ITE-IDY, IEIJ-SSL, SID-JC, IEE-EDD [detail] | 2018-01-26 09:40 |
Shizuoka | Shizuoka Univ., Hamamatsu | Luminescent properties in ZnO thin films prepared by mist-CVD method Katsuya Nakada, Takeshi Kanno, Yoshiki Saito, Shogo Saeki, Satoshi Yamaji, Haruki Fukada, Atsushi Yamaguchi (KIT) |
[more] | |
| RECONF | 2011-09-26 10:45 |
Aichi | Nagoya Univ. | Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1. Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications)  RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] | RECONF2011-22 pp.1-6 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Silent Large Datapath : A Ultra Low Power Accelarater Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78 |
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded systems. By using a... [more] |
VLD2010-109 CPSY2010-64 RECONF2010-78 pp.169-174 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79 |
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] | VLD2010-110 CPSY2010-65 RECONF2010-79 pp.175-180 |
| RECONF | 2010-05-13 14:55 |
Nagasaki | A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2010-4 |
Recently, since a mobile device is required to provide various functions, a lot of specialized hardware modules must be... [more] |
RECONF2010-4 pp.19-24 |
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| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 09:25 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2009-85 CPSY2009-67 RECONF2009-70 |
[more] | VLD2009-85 CPSY2009-67 RECONF2009-70 pp.101-106 |
| RECONF | 2009-09-17 16:05 |
Tochigi | Utsunomiya Univ. | Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.) RECONF2009-26 |
One of benefit of coarse-grained dynamically reconfigurable processor arrays (DRPAs) is its low dynamic power consump... [more] |
RECONF2009-26 pp.43-48 |
| RECONF | 2009-05-14 13:30 |
Fukui | Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) RECONF2009-2 |
Dynamically Reconfigurable Processor Array(DRPA) has been received an attention as a flexible and power efficient off-lo... [more] | RECONF2009-2 pp.7-12 |
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| RECONF | 2008-09-26 11:00 |
Okayama | Okayama Univ. | Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34 |
Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loadi... [more] | RECONF2008-34 pp.69-74 |
| RECONF | 2008-05-23 09:00 |
Fukushima | The University of Aizu | Designing And Evaluating Dynamically Reconfigurable Processor with Power Gating Technique Yoshiki Saito (Keio Univ.), Toshiaki Shirai (Shibaura Inst.), Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami (Shibaura Inst.), Hideharu Amano (Keio Univ.) RECONF2008-10 |
A dynamically reconfigurable processor achieves high performance making the best use of high degree of parallelism with ... [more] | RECONF2008-10 pp.55-60 |
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