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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2010-05-19
16:10		 Fukuoka Kitakyushu International Conference Center Highly Accurate Approximate Methods for Soft Error Tolerance Estimation for Sequential Circuits
Naoki Shirobayashi, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2010-2		 Soft error tolerance estimation method is necessary for soft error
aware logic designs. There is an exact method has b... [more]		 VLD2010-2
pp.25-30
VLD, IPSJ-SLDM 2010-05-19
16:35		 Fukuoka Kitakyushu International Conference Center An Approximate Method for Steady State Probability Calculation based on FSM Splitting
So Hasegawa, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2010-3		 An exact method evaluate soft error tolerance with Markov model
has been proposed. This method, however, is difficult t... [more]		 VLD2010-3
pp.31-36
VLD 2010-03-12
13:55		 Okinawa   An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-126		 Soft error tolerance estimation method is necessary for the soft error aware logic design. We proposed an estimation met... [more] VLD2009-126
pp.163-168
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-03
10:00		 Kochi Kochi City Culture-Plaza An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-49 DC2009-36		 Soft error tolerance evaluation method is necessary for the soft error aware logic design. An evaluation method with Mar... [more] VLD2009-49 DC2009-36
pp.55-60
VLD 2009-09-24
15:50		 Osaka Osaka University On accelleration of SER analysis for sequential circuits using implicit enumeration
Yusuke Matsunaga, Yusuke Akamine (Kyushu Univ.) VLD2009-34		  [more] VLD2009-34
pp.31-36
DC, CPSY 2009-04-21
16:35		 Tokyo Akihabara Satellite Campus, Tokyo Metropolitan Univ. Pulse Propagation Analysis for SER Evaluation of Logic Circuits
Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ) CPSY2009-9 DC2009-9		 As a transistor feature size scales down in recent years, soft error tends to increase. In logic circuits, a pulse genar... [more] CPSY2009-9 DC2009-9
pp.49-54
VLD 2009-03-12
11:05		 Okinawa   High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit
Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT) VLD2008-143		 (To be available after the conference date) [more] VLD2008-143
pp.101-106
 Results 1 - 7 of 7  /   
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