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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD 2024-01-29
17:00		 Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)		 Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis -- Toward comparative evaluation of latch-based and flip-flop-based circuits --
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-90 RECONF2023-93		 As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms... [more] VLD2023-90 RECONF2023-93
pp.59-64
RECONF, VLD 2024-01-29
17:25		 Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)		 Comparison of latch-based circuit and flip-flop-based circuit in actual device
Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-91 RECONF2023-94		 The comparison results of current consumption, maximum operating frequency (Fmax) characteristics and minimum operating ... [more] VLD2023-91 RECONF2023-94
pp.65-70
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