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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2013-05-16
16:25		 Fukuoka Kitakyushu International Conference Center SoC System Design Methodology with Fully-Coherent Cache
Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10		 As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the en... [more] VLD2013-10
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-29
13:25		 Miyazaki NewWelCity Miyazaki A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs
Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-44		 We proposed previously Linear Array Pipeline Processor (LAPP), which can be used to map an inner
loop of conventional V... [more]		 CPSY2011-44
pp.9-14
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