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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2008-07-17
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention
Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] SDM2008-136 ICD2008-46
pp.47-52
ICD, ITE-CE 2006-12-15
11:15
Hiroshima   Low Power SOC Design using Partial-Trench-Isolation ABC SOI for sub-100-nm LSTP technology
Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yoshihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi (Renesas)
 [more] ICD2006-163
pp.115-119
SIP, ICD, IE, IPSJ-SLDM 2005-10-20
16:30
Miyagi Ichinobo, Sakunami-Spa A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] SIP2005-113 ICD2005-132 IE2005-77
pp.107-112
ICD, SDM 2005-08-18
16:20
Hokkaido HAKODATE KOKUSAI HOTEL SOI; the Trump Card of SOCs in Sub. 50-nm Era -- Techniques that SOI Conquers Bulk! --
Tadayoshi Enomoto (Chuo Univ.), Takakuni Douseki (NTT), Kazutami Arimoto (Renesas), Jiroh Ida (Oki), Takashi Ipposhi (Renesas), Kazuhiko Miki (Toshiba), Masanao Yamaoka (Hitachi), Makoto Yoshimi (SOITEC)
(Advance abstract in Japanese is available) [more] SDM2005-142 ICD2005-81
pp.85-90
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