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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2014-01-28
15:00		 Kyoto Kyoto Univ. Tokeidai Kinenkan [Poster Presentation] An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory
Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST) ICD2013-125		 Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] ICD2013-125
p.59
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-30
10:30		 Miyazaki NewWelCity Miyazaki Immunity Evaluation of SRAM Core Using DPI with On-Chip Diagnosis Structures
Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa (Kobe Univ.), Hidehiro Takata, Koji Nii (Renesas Electronics Corp.), Makoto Nagata (Kobe Univ.) CPM2011-165 ICD2011-97		  [more] CPM2011-165 ICD2011-97
pp.85-90
ICD 2010-12-16
15:10		 Tokyo RCAST, Univ. of Tokyo [Poster Presentation] Evaluation of power noise in SRAM core
Taku Toshikawa, Tsubasa Masui, Takuya Sawada, Makoto Nagata (Kobe Univ.) ICD2010-112		 Power noise of SRAM operation is evaluated with a test chip fabricated in a 90-nm CMOS technology. The chip includes on-... [more] ICD2010-112
pp.85-88
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-29
11:00		 Fukuoka Kyushu University Evaluation of on-chip power noise generation and injection in SRAM core
Takuya Sawada, Taku Toshikawa, Tsubasa Masui (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST) CPM2010-125 ICD2010-84		 The noise tolerance of SRAM was evaluated by evaluating the power supply noise generation, and injecting the RF noise i... [more] CPM2010-125 ICD2010-84
pp.7-12
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