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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2014-03-04
13:20		 Okinawa Okinawa Seinen Kaikan [Invited Talk] Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm
Shuhei Sota (Toshiba Microelectronics), Taiga Uno, Masanari Kajiwara, Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Ryota Aburada, Toshiya Kotani (Toshiba), Kei Nakagawa, Tamaki Saito (Toshiba Microelectronics) VLD2013-148		 Under the low-k1 lithography process, many hotspots are generated and their reduction is an urgent issue for mass produc... [more] VLD2013-148
p.85
VLD 2014-03-04
14:40		 Okinawa Okinawa Seinen Kaikan Self-Aligned Double and Quadruple Patterning-Aware Grid Routing
Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-151		 Self-Aligned Double and Quadruple Patterning (SADP, SAQP) are leading candidates for sub-$20~nm$ and sub-$14~nm$ node an... [more] VLD2013-151
pp.99-104
VLD 2014-03-04
15:05		 Okinawa Okinawa Seinen Kaikan Exposure source optimization by clustering for lithography
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-152		 In lithography, we generate patterns on a wafer through a photomask,
where patterns generated have to be close to ideal... [more]		 VLD2013-152
pp.105-110
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-29
13:00		 Miyazaki NewWelCity Miyazaki Layout Methodology for Self-Alinged Double Patterning
Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba) VLD2011-76 DC2011-52		 We propose a new layout method for the damascene process of
self-aligned double patterning (SADP).
In this method, w... [more]		 VLD2011-76 DC2011-52
pp.141-146
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