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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
13:20		 Kagoshima   NoC routers using the marching memory through type
Ryota Yasudo, Takahiro Kagami, Hideharu Amano (Keio Univ.), Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu (Renesas), Tadao Nakamura (Keio Univ.) CPSY2013-71		 We propose a NoC(Network-on Chip) router using the marching memory through type in order to reduce the power consumption... [more] CPSY2013-71
pp.71-76
ICD, ITE-IST 2013-07-05
11:25		 Hokkaido San Refre Hakodate 0.5V Start-up Feed Forward Controlled Single-Inductor Dual-Output(SIDO) Boost On-chip DC-DC Converter for Sensor Network Application
Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu (Renesas Electronics) ICD2013-36		 An on-chip low power single-inductor dual-output DC-DC converter is proposed for battery and solar cell operating sensor... [more] ICD2013-36
pp.75-80
ICD 2010-04-22
10:50		 Kanagawa Shonan Institute of Tech. A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3		 We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] ICD2010-3
pp.13-16
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