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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2010-04-22 15:45 |
Kanagawa |
Shonan Institute of Tech. |
A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10 |
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] |
ICD2010-10 pp.53-57 |
ICD |
2007-04-12 13:00 |
Oita |
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[Invited Talk]
2-Mb SPRAM (SPin-transfer torque RAM) with Bit-by-bit Bi-Directional Current Write and Parallelizing-Direction Current Read Riichiro Takemura, Takayuki Kawahara, Katsuya Miura (Hitachi), Jun Hayakawa (Hitachi/Tohoku Univ.), Shoji Ikeda, Young Min LEE, Ryutaro Sasaki (Tohoku Univ.), Yasushi Goto, Kenchi Ito (Hitachi), Toshiyasu Meguro, Fumihiro Matsukura (Tohoku Univ.), Hiromasa Takahashi (Hitachi/Tohoku Univ.), Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2007-6 |
A 1.8-V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2 µm logic process with MgO tunneling barrier cell demo... [more] |
ICD2007-6 pp.29-34 |
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