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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, ICD [detail] 2021-10-19
10:00		 Online Online Evaluations of tamper resistance by Wave-FF for Power Analysis Attack on AES
Tomoaki Ukezono (Fukuoka Univ.) HWS2021-41 ICD2021-15		 Dual-Rail design represented by WDDL can be mentioned as a countermeasure against information leakage from power consump... [more] HWS2021-41 ICD2021-15
pp.1-6
CPSY, DC 2014-04-25
14:00		 Tokyo   Construction of Design Environment for Asynchronous Circuits using DDL Cell Library
Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2		 As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] CPSY2014-2 DC2014-2
pp.3-8
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-27
10:20		 Kagoshima   Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM
Shintaro Ukai, Tsunato Nakai, Toshiki Kitamura, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-111 ICD2013-88		 Tamper-resistant devices require to protect cryptographic circuit from side-channel attacks such as power analysis (PA) ... [more] CPM2013-111 ICD2013-88
pp.19-24
VLD, ICD, DC, IPSJ-SLDM 2005-11-30
17:00		 Fukuoka Kitakyushu International Conference Center Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) 		As the VLSI technology advances, delay variations will become more serious.
Delay insensitive asynchronous dual-rail ci... [more]		 VLD2005-60 ICD2005-155 DC2005-37
pp.37-42
 Results 1 - 4 of 4  /   
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