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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 16:15 |
Miyagi | A Low Supply Voltage Six-Transistor CMOS SRAM Employing Adaptively Lowering Memory Cell Supply Voltage for "Write" Operation Nobuaki Kobayashi (Nagaoka Univ. of Tech.), Ryusuke Ito, Tadayoshi Enomoto (Chuo Univ.)  VLD2014-66 ICD2014-59 IE2014-45 |
We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, not only to expand b... [more] | VLD2014-66 ICD2014-59 IE2014-45 pp.33-38 |
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| SDM, ICD | 2011-08-26 15:05 |
Toyama | Toyama kenminkaikan | A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60 |
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] | SDM2011-92 ICD2011-60 pp.109-114 |
| ITE-MMS, MRIS | 2010-12-09 16:00 |
Ehime | Ehime Univ. | Write-margin Estimation of BPM using Static-tester Kazuki Shirahata (RIEC,Tohoku Univ.), Hideki Saga (CRL,Hitachi,Ltd/RIEC,Tohoku Univ.), Kenji Miura, Takehito Shimatsu, Hajime Aoi, Hiroaki Muraoka (RIEC,Tohoku Univ.) MR2010-47 |
Bit patterned medium (BPM) recording is widely studied as a future perpendicular magnetic recording technology. Only sma... [more] | MR2010-47 pp.39-43 |
| ITE-MMS, MRIS | 2010-10-14 13:15 |
Akita | Akita Research and Development Center | [Invited Talk]
Simulations of heat assisted recording in bit patterned media Simon Greaves, Hiroaki Muraoka (Tohoku Univ.), Yasushi Kanai (Niigata Inst. of Tech.) MR2010-22 |
Heat assisted recording on bit patterned media was simulated. The write margins for areal recording densities up to 9 Tb... [more] | MR2010-22 pp.1-6 |
| MRIS, ITE-MMS | 2010-06-10 14:30 |
Miyagi | RIEC Tohoku Univ. | Performance evaluation of LDPC coding and iterative decoding system based on write-process in R/W channel using BPM Yasuaki Nakamura, Yoshihiro Okamoto, Hisashi Osawa (Ehime Univ.), Hajime Aoi, Hiroaki Muraoka (Tohoku Univ.) MR2010-3 |
In this report, we evaluate the performance of the write-margin for the low-density parity-check (LDPC) coding and itera... [more] | MR2010-3 pp.21-26 |
| MRIS, ITE-MMS | 2008-12-12 09:30 |
Ehime | Ehime University | A Study of Magnetostatic Interaction and Write Margin of Staggered Patterned Media Naomichi Degawa, Simon Greaves, Hiroaki Muraoka (RIEC, Tohoku Univ.), Yasushi Kanai (Niigata Inst. of Tech.) MR2008-46 |
The assignment of bit-patterned media (BPM) with high recording density is to reduce interference of magnetostatic inter... [more] | MR2008-46 pp.49-53 |
| CPM | 2005-10-21 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | New Method for Adjusting Write Strategy using Sequenced Amplitude Margin Yoshihisa Adachi, Atsushi Etoh, Mitsuo Ishii, Shigemi Maeda, Kunio Kojima (Sharp) |
We proposed a new method for adjusting write strategy in partial response maximum likelihood systems. It utilizes novel ... [more] | CPM2005-147 pp.19-23 |
| ICD | 2005-04-14 09:00 |
Fukuoka | A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL) |
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-Vt NMOS transistors us... [more] | ICD2005-1 pp.1-6 |
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| ICD | 2005-04-14 09:30 |
Fukuoka | Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] | ICD2005-2 pp.7-12 |
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