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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
09:25		 Fukuoka Centennial Hall Kyushu University School of Medicine Routability-oriented Common-Centroid Capacitor Array Generation
Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2012-89 DC2012-55		 We address layout generation of on-chip matched capacitors with the high relative accuracy. Unit capacitors are placed i... [more] VLD2012-89 DC2012-55
pp.171-175
SANE 2012-10-11
14:00		 Overseas The SONGDO CONVENSIA, Incheon Korea Feasibility Study on Supercapacitors as Alternative to Secondary Batteries in Spacecraft Power Systems
Masatoshi Uno, Akio Kukita (JAXA) SANE2012-88		 The feasibility of supercapacitors (SCs), including electric double-layer capacitors (EDLCs) and lithium-ion capacitors ... [more] SANE2012-88
pp.181-186
SANE 2012-06-28
14:55		 Ibaraki Tsukuba Space Center, JAXA Feasibility Study on Spacecraft Power System Using Lithium-Ion Capacitor
Masatoshi Uno, Akio Kukita (JAXA) SANE2012-26		 The feasibility of the spacecraft power system using lithium-ion capacitors (LICs) as its energy storage source is discu... [more] SANE2012-26
pp.31-36
EMCJ 2011-04-22
14:35		 Hyogo University of Hyogo Decoupling of Power Distribution Network to Improve Tolerance of Side-Channel Attacks in Cryptographic FPGA
Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2011-4		 Side-channel attack is a cryptanalytic attack by means of radio frequency (RF) power current from cryptographic IC. On-b... [more] EMCJ2011-4
pp.19-24
ICD, IPSJ-ARC 2008-05-14
11:15		 Tokyo   Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates
Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) ICD2008-28		 Multi-Context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching betw... [more] ICD2008-28
pp.57-62
ICD 2006-04-13
13:00		 Oita Oita University [Special Invited Talk] Techniques and Scaling Scenario for Chain FeRAM
Daisaburo Takashima (Toshiba) 		A chain FeRAM architecture is the best solution to realize high-density, high-speed and low power nonvolatile memory. In... [more] ICD2006-6
pp.31-36
 Results 1 - 6 of 6  /   
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