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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS | 2023-04-14 13:45 |
Oita | (Primary: On-site, Secondary: Online) |
Fundamental Study on the effect of the Number of RNS Bases on the Side-channel Information Leakage from Modular Multiplier Daisuke Fujimoto, Rikuo Haga, Yuichi Hayashi (NAIST)  HWS2023-2 |
In public-key cryptography, the Residue Number System (RNS) has been proposed as a hardware implementation approach that... [more] | HWS2023-2 pp.6-8 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 13:45 |
Online | Online | Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS Hiroyuki Tsubouchi, Mitsunaga Kinjo, Katsuhiko Shimabukuro (Univ. of the Ryukyus) SDM2021-40 ICD2021-11 |
Modulo operations are required in RNS (Residue Number System) which enables to perform highly parallel computation. Also... [more] | SDM2021-40 ICD2021-11 pp.54-57 |
| HWS, ISEC, SITE, ICSS, EMM, IPSJ-CSEC, IPSJ-SPT [detail] | 2018-07-26 15:25 |
Hokkaido | Sapporo Convention Center | A Study on Systematic Insertion of Hardware Trojan Based on Path Delay Akira Ito, Rei Ueno, Naofumi Homma, Takafumi Aoki (Tohoku Univ.) ISEC2018-44 SITE2018-36 HWS2018-41 ICSS2018-47 EMM2018-43 |
This paper presents a non-reversible and analytical method for inserting a path delay hardware Trojan (PDHT). The conven... [more] | ISEC2018-44 SITE2018-36 HWS2018-41 ICSS2018-47 EMM2018-43 pp.349-356 |
| SCE | 2014-01-24 13:40 |
Tokyo | Kikaishinkou-kaikan Bldg. | Comparison of the final addition circuit in SFQ parallel multiplier with a tree structure partial product adder circuit Akifumi Yamada, Takeshi Onomi, Koji Nakajima (Tohoku Univ.) SCE2013-52 |
A single flux quantum (SFQ) circuit is capable of high-speed operation in a few 10 GHz, and it has a big advantage compa... [more] | SCE2013-52 pp.101-104 |
| EMCJ | 2013-04-12 11:55 |
Okayama | Okayama Univ. | Low Power CSSAL Bit-Parallel Multiplier over GF(2^4) in 0.18 um CMOS Technology Cancio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) EMCJ2013-3 |
本論文は，我々が提案したセキュア断熱的差動論理論理回路CSSALを用いて，ガロア体GF(2^4)を並列乗算器にて構成し，従来の2N-2N2P断熱論理とTDPLのそれらをポストレイアウトシミュレーションにて比較した結果を示す．Cadence ... [more] | EMCJ2013-3 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2008-77 DC2008-45 |
In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such ... [more] | VLD2008-77 DC2008-45 pp.103-108 |
| COMP | 2007-12-14 14:50 |
Hiroshima | Hiroshima University | Evaluation of Hardware Algorithm Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) COMP2007-51 |
Computation time of hardware algorithms has been evaluated with the number of levels of the combinational circuit model.... [more] | COMP2007-51 pp.23-28 |
| CAS, SIP, VLD | 2007-06-22 13:20 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | Arithmetic Module Generation Using Optimized Parallel Prefix Adders Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Totech) CAS2007-27 VLD2007-43 SIP2007-57 |
This paper presents an arithmetic module generator using parallel prefix adders. In the proposed system, parallel prefix... [more] | CAS2007-27 VLD2007-43 SIP2007-57 pp.49-54 |
| RECONF | 2005-05-13 15:45 |
Kyoto | Kyoto University | An Analysis of Fixed Point Arithmetic for DRP Miwa Miyata, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
Since Dynamically Reconfigurable Processor (DRP) has a lot of integer arithmetic units and small scale distributed memor... [more] | RECONF2005-25 pp.61-66 |
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