Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
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ICD2005-13
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy)
pp. 1 - 6
ICD2005-14
High Density and Low Power Nonvolatile FeRAM Memory Cell Architecture
Takashi Miki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Yasushi Gohou, Eiji Fujii (Matsushita Electric Industrial Co., Ltd.)
pp. 7 - 12
ICD2005-15
Burst-Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM
Ryo Fukuda, Kenji Kobayashi (Toshiba Corp.), Masashi Akamatsu, Minoru Kaihatsu, Atsushi Tamura, Kazuo Taniguchi (Sony Corp.), Yohji Watanabe (Toshiba Corp.)
pp. 13 - 17
ICD2005-16
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell
-- High Speed and Low-Power Operation by Using Dual-Wordline Scheme --
Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL)
pp. 19 - 24
ICD2005-17
Application of Bank-Based Multiport Memory to the Microprocessor Caches
Koh Johguchi, Zhaomin Zhu (Hiroshima Univ.), Tai Hirakawa (Hiroshima City Univ.), Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.), Tetsuo Hironaka, Kazuya Tanigawa (Hiroshima City Univ.)
pp. 25 - 30
ICD2005-18
Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes
Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi)
pp. 31 - 36
ICD2005-19
New Development of Neutron-induced Soft-Error Simulation Technology
Taiki Uemura, Yoshiharu Tosaka, Yoshio Ashizawa, Hideki Oka, Shigeo Satoh (Fujitsu lab.)
pp. 37 - 42