IEICE Technical Report

Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380

vol. 105, no. 287

Reconfigurable Systems

Workshop Date : 2005-09-15 / Issue Date : 2005-09-08

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RECONF2005-30
Place and Route Processing in Back End Compiler for Reconfigurable Architecture 'PARS'
Ryuji Hada, Takeshi Fukuda, Kazuya Tanigawa, Akira Kojima, Tetsuo Hironaka (HCU)
pp. 1 - 6

RECONF2005-31
OS Function and Programing Model for Reconfigurable Architecture
Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 7 - 12

RECONF2005-32
PELOC:An Automatic Place-and-Route Tool for Dynamically Reconfigurable FPGAs -- Application to the Flexible Processor --
Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Khan Ashfaquzzaman, Daisuke Iwama, Hiroaki Kanto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi (Tohoku Univ.)
pp. 13 - 18

RECONF2005-33
On LUT cascade realizations of FIR filters using arithmetic decomposition
Tsutomu Sasao (Kyutech), Yukihiro Iguchi, Takahiro Suzuki (Meiji Univ.)
pp. 19 - 24

RECONF2005-34
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices
Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano (Keio Univ.)
pp. 25 - 30

RECONF2005-35
Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor
Yohei Hasegawa, Hideharu Amano, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan (Keio Univ.)
pp. 31 - 36

RECONF2005-36
A Simulation Platform for Designing Self-Reconfigurable Architecture and its application for Study on Coarse-Grained Devices
Shin'ichi Kouyama, Futoshi Morie, Kentaro Nakahara (Kyoto Univ.), Tomonori Izumi (Ritsumeikan Univ.), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.)
pp. 37 - 42

RECONF2005-37
Development of a partial reconfiguration controller for an embedded processor FPGA
Isao Sakamoto, Takanori Susaki, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 43 - 48

RECONF2005-38
Feasibility study on a run-time reconfigurable MPEG-2 decoder using functional separation
Takeru Kisanuki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 49 - 54

RECONF2005-39
Control Mechanism of the FPGA-Based Biochemical Simulator ReCSiP
Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Toshinori Kojima, Yuri Nishikawa (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)
pp. 55 - 60

RECONF2005-40
Building of the SBML System for an FPGA-based Biochemical Simulator
Yow Iwaoka, Yasunori Osana, Masato Yoshimi, Toshinori Kojima, Yuri Nishikawa (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)
pp. 61 - 66


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan