Print edition: ISSN 0913-5685
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
VLD2006-14
Area/delay Estimation for Application Processor
Daisuke Yamazaki, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 1 - 6
VLD2006-15
Modeling of Layout Dependent Copper Electrochemical Plating
Daisuke Fukuda, Hidetoshi Matsuoka, Toshiyuki Shibuya (FUJITSU LABORATORIES LTD.)
pp. 7 - 12
VLD2006-16
A CMOS Current Reference Independent of Deviation of Threshold Voltage
Masashi Negishi (Chuo Univ.), Kawori Takakubo (Meiji Univ.), Hajime Takakubo (Chuo Univ.)
pp. 13 - 18
VLD2006-17
A Design of Genotypes for Path Generation Using Genetic Algorithms
Jun Inagaki, Toshitada Mizuno, Tomoaki Shirakawa, Tetsuo Shimono (Hokkaido Tokai Univ.)
pp. 19 - 23
VLD2006-18
Solution Space Reduction of Sequence Pairs using Model Placement
Mineo Kaneko (JAIST)
pp. 25 - 28
VLD2006-19
Sequence-Pair Based Compaction under Equi-Length Constraint
Takehiko Matsuo (Univ. of Kitakyushu), Keiji Kida (Jedat), Tetsuya Tashiro, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 29 - 34
VLD2006-20
Re-placement Method for Circuit Modification
Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 35 - 40
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.