Print edition: ISSN 0913-5685
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VLD2006-1
Online FPGA Placement Using I/O Routing Information
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita (NAIST), Kazuo Nakajima (Univ. of Maryland), Katsumasa Watanabe (NAIST)
pp. 1 - 6
VLD2006-2
Dynamic Reconfigurable Wiring Architecture and Its Application to Hardware Mapping
Shinji Kimura (Waseda Univ.)
pp. 7 - 12
VLD2006-3
A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
pp. 13 - 18
VLD2006-4
Automatic Generation of Custom Instructions with Memory Access and Resource Sharing
Kenshu Seto, Masahiro Fujita (Univ. of Tokyo)
pp. 19 - 24
VLD2006-5
[Invited Talk]
Configurable Processor Design Environment ASIP Meister
Masaharu Imai, Ittetsu Taniguchi, Yoshinori Takeuchi, Keishi Sakanushi (Osaka Univ.)
pp. 25 - 30
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.