IEICE Technical Report

Print edition: ISSN 0913-5685

VLSI Design Technologies

Workshop Date : 2006-05-12 / Issue Date : 2006-05-05

VLD2006-6
Bottom-up Equivalence Checking for SpecC Programs
Subash Shankar (City Univ. of New York), Masahiro Fujita (Univ. of Tokyo)
pp. 1 - 6

VLD2006-7
An Approach to Formal Equivalence Checking by Symbolic Simulation between Behavioral and RTL Designs
Takeshi Matsumoto, Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo)
pp. 7 - 12

VLD2006-8
An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel
Takatomi Wada, Yasushi Hibino (JAIST)
pp. 13 - 18

VLD2006-9
Efficient generation method of indirect implication on ATPG
Masayoshi Yoshimura (FLEETS), Seiji Kajihara (KIT), Yusuke Matsunaga (Kyushu University)
pp. 19 - 23

VLD2006-10
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST)
pp. 25 - 30

VLD2006-11
Reduction of Equalizing Circuit Area for 8-VSB Demodulator Using the Result of Correlation Operation
Kazumi Kawashima, Yusuke Konishi, Yusuke Hashiguchi, Yuu Yamamoto, Masahiro Numa (Kobe Univ.)
pp. 31 - 36

VLD2006-12
Delay and Power Consumption of Integer Multipiler -- Comparison of Wallace and Dadda tree --
Masayoshi Tachibana (KUT)
pp. 37 - 40

VLD2006-13
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yang Yuan (Xi'an Univ. of Technology), Kosuke Tarumi, Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
pp. 41 - 46

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan