Print edition: ISSN 0913-5685
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VLD2006-51
A methodology of generating verification scenarios from specification
Ryosuke Oishi, Akio Matsuda, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs. LTD.)
pp. 1 - 4
VLD2006-52
Equivalence Checking using a Decidable Subclass of First-Order-Logic under Equivalence Constraints
Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.)
pp. 5 - 10
VLD2006-53
Bounded Model Checking for Assertions including Dynamic Local Variables
Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.)
pp. 11 - 16
VLD2006-54
Formal Verification Method for Arithmetic Circuits and Its Evaluation
Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Totech)
pp. 17 - 22
VLD2006-55
A Method of Test Plan Generation in Hierarchical Test Based on Balanced Structure
Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 23 - 28
VLD2006-56
Test Compression/Decompression with the Decoding Function in Multimedia Cores
Yukinori Setohara, Yusuke Nakashima, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 29 - 34
VLD2006-57
Test relaxation for N-detection test patterns in broad-side delay testing
Kenjiro Taniguchi (Kyushu Inst. of Tech.), Kohei Miyase (JST), Seiji Kajihara, Xiaoqing Wen (Kyushu Inst. of Tech.)
pp. 35 - 40
VLD2006-58
Decision Diagram Data Structure to Represent Quantum Circuit
Shigeru Yamashita (NAIST), D. Michael Miller (Univ. of Victoria)
pp. 41 - 46
VLD2006-59
Depth-Optimum and Area-Optimal Technology Mapping for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 47 - 52
VLD2006-60
Asymmetric Slope Differential Logic with High-Speed and Low-Power Operation Modes
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki (AIL)
pp. 53 - 58
VLD2006-61
Test Scheduling for SoCs with Built-In Self-Repairable Memory Cores
Yusuke Fukuda, Tomokazu Yoneda, Hideo Fujiwara (NAIST)
pp. 59 - 64
VLD2006-62
A Self-Test of Dynamically Reconfigurable Processors
Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 65 - 70
VLD2006-63
Proposal of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-data Implementation
Naohiro Hamada, Takao Konishi, Hiroshi Saito (The Univ. of Aizu), Tomohiro Yoneda (NII), Takashi Nanya (The Univ. of Tokyo)
pp. 71 - 76
VLD2006-64
A Basic Study on Data Path Synthesis Considering Delay Variation
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
pp. 77 - 82
VLD2006-65
Computational Complexity of Simultaneous Optimization of Control Schedule and Skew in Datapath Synthesis
Takayuki Obata, Mineo Kaneko (JAIST)
pp. 83 - 88
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.