Print edition: ISSN 0913-5685
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
ICD2006-40
A Case for Hot-Path-based Branch Prediction
Kosuke Tsuiji, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 1 - 6
ICD2006-41
A Low-Power, Reliable Datapath by Reusing Execution Results
Yosuke Hashiguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ)
pp. 7 - 12
ICD2006-42
Reducing Energy Consumption of the Dynamic Scheduling Logic by Instruction Grouping
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo)
pp. 13 - 18
ICD2006-43
Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection
Jun Yao, Hajime Shimada (Kyoto Univ.), Yasuhiko Nakashima (NAIST), Shin-ichiro Mori (Fukui Univ.), Shinji Tomita (Kyoto Univ.)
pp. 19 - 24
ICD2006-44
[Special Invited Talk]
The need of a collaboration between the computer architecture and the integrated circuit technology
Hisashige Ando (Fujitsu Ltd.)
pp. 25 - 30
ICD2006-45
50% power reduction in H.264/AVC HDTV decoder LSI by dynamic voltage/frequency scaling with elastic pipeline architecture
Kentaro Kawakami (Kobe Univ.), Jun Takemura (Renesas), Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
pp. 31 - 36
ICD2006-46
Physical Register Access Analysis for Temperature-Aware Microarchitecture
Toshinori Sato (Kyushu Univ.), Yuji Kunitake, Akihiro Chiyonobu (Kyushu Inst. Tech.)
pp. 37 - 42
ICD2006-47
Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka (Kyushu Inst. Tech.), Toshinori Sato (Kyushu Univ.)
pp. 43 - 48
ICD2006-48
Design for Testability of Software-Based Self-Test for Processors
Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST)
pp. 49 - 54
ICD2006-49
[Special Invited Talk]
Discussing the national next-generation supercomputer from the viewpoint of LSI technology and computer architecture
Kazuaki Murakami (Kyushu Univ.)
p. 55
ICD2006-50
Voltage/Current-Control-Based Low-Power Design of a Multiple-Valued Reconfigurable VLSI
Nobuaki Okada, Haque Mohammad Munirul, Michitaka Kameyama (Tohoku Univ.)
pp. 57 - 61
ICD2006-51
Dynamically Reconfigurable Architecture for Road Extraction
Sunge Lee, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 63 - 67
ICD2006-52
A Reconfigurable Functional Unit for Adaptable Custom Instructions
Hamid Noori (Kyushu Univ.), Farhad Mehdipour (Amirkabir Univ. of Tech.), Kazuaki Murakami, Koji Inoue (Kyushu Univ.), Morteza Saheb Zamani (Amirkabir Univ. of Tech.)
pp. 69 - 74
ICD2006-53
[Special Invited Talk]
Architecture and Circuit, How to Collaborate ?
Naoki Nishi (NEC)
pp. 75 - 76
ICD2006-54
A Superscalar employing Instruction Decomposition for ARM Architecture
Yasuhiko Nakashima (NAIST)
pp. 77 - 82
ICD2006-55
A VLIW Single-Chip Multi-Processor for Multimedia processing
Masahiko Toichi, Atsuhiro Suga, Fumihiko Hayakawa, Shinichiro Tago, Satoshi Imai, Atsushi Tanaka (Fujitsu Lab)
pp. 83 - 88
ICD2006-56
Design of a High Performance Vision Processor with Shared Memory Multi-SIMD Architecture
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa (The University of Tokyo)
pp. 89 - 94
ICD2006-57
Optimal Memory Allocation for Image Processors
Masanori Hariyama (Tohoku Univ.), Yasuhiro Kobayashi (Oyama National College of Tech.), Michitaka Kameyama (Tohoku Univ.)
pp. 95 - 100
ICD2006-58
A Virtual-Channel Free Mapping for On-Chip Torus Networks
Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 101 - 106
ICD2006-59
[Panel Discussion]
How do we create combining architecture and integrated circuits?
Kunio Uchiyama (Hitachi, Ltd.,)
p. 107
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.