IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2007-11-20 / Issue Date : 2007-11-13

VLD2007-70
2-Step Test Data Compression using Scan FF with Two Pattern Testability
Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.)
pp. 1 - 6

VLD2007-71
A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing
Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT)
pp. 7 - 12

VLD2007-72
An optimization of thru trees for test generation based on acyclical testability
Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 13 - 18

VLD2007-73
An Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic
Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.)
pp. 19 - 24

VLD2007-74
A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
pp. 25 - 29

VLD2007-75
An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
pp. 31 - 36

VLD2007-76
A process-variation-aware low-power technique using current control
Kyun-dong Kim, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo)
pp. 37 - 42

VLD2007-77
Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit
Yoshinobu Toyoda, Kenta Kido, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.)
pp. 43 - 48

VLD2007-78
Comparison of Standard Cell Non-linear Asynchronous Pipelines
Chammika Mannakkara, Tomohiro Yoneda (NII)
pp. 49 - 54

VLD2007-79
An On-Chip Bus Architecture for Post-Fabrication Timing Calibration
Masaki Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
pp. 55 - 60

VLD2007-80
Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing
Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.)
pp. 61 - 66

VLD2007-81
Initial Evaluation of FIR Filter Based on Digit-Serial Computation
Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
pp. 67 - 72

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan