IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Silicon Device and Materials

Workshop Date : 2008-03-14 / Issue Date : 2008-03-07

SDM2007-273
15nm Planar Bulk SONOS-type Memory with Double Junstion Tunnel Layers
Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba)
pp. 1 - 6

SDM2007-274
Fabrication and characterization of oxide-channel ferroelectric-gate nonvolatile memory devices
Hiroshi Shibata, Tomohiro Oiwa, Eisuke Tokumitsu (Tokyo Tech)
pp. 7 - 12

SDM2007-275
Characteristics of metal-ferroelectric-insulartor-semiconductor structures based on poly(vinylidene fluoride-trifluoroethylene)
Joo Won Yoon, Shun-ichiro Ohmi, Hiroshi Ishiwara (Tokyo Inst. of Tech)
pp. 13 - 16

SDM2007-276
Compliant Micro-Bumps for 3D Stacked-Chip LSIs with High Density Interconnection Implemented at Low Temperature
Naoya Watanabe (Kumamoto TIF), Yutaka Iwasaki, Tanemasa Asano (Kyushu Univ.)
pp. 17 - 20

SDM2007-277
Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding
Naotaka Tanaka, Yasuhiro Yoshimura, Michihiro Kawashita (Hitachi), Toshihide Uematsu, Takahiro Naitoh, Takashi Akazawa (Renesas)
pp. 21 - 26

SDM2007-278
Realistic future trend of advanced non-volatile memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory
Shigeyoshi Watanabe (SIT)
pp. 27 - 32

SDM2007-279
New design technology of independent-gate controlled Double-Gate transistor for LSI
Yu Hiroshima, Keisuke Okamoto, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 33 - 38

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan