IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2008-09-29 - 2008-09-30 / Issue Date : 2008-09-22

VLD2008-47
[Invited Talk] Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling
Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology)
pp. 1 - 6

VLD2008-48
A DFG Mapping Algorithm for Flexible Engine/Generic ALU Array
Masayuki Honma, Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.)
pp. 7 - 12

VLD2008-49
FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.)
pp. 13 - 18

VLD2008-50
Schedulable Resouce Binding under Skew Optimization
Takayuki Obata, Mineo Kaneko (JAIST)
pp. 19 - 24

VLD2008-51
Delay Variation-Aware Datapath Synthesis Based on Register Clustering
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
pp. 25 - 30

VLD2008-52
Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print)
pp. 31 - 36

VLD2008-53
[Invited Talk] On the Order Statistics Applications to EDA, including Non Parametric Statistical Static Timing Analysis
Masanori Imai (STARC/Tokyo Inst. Tech.)
pp. 37 - 42

VLD2008-54
Overlap-aware Analytical Placement Based on Stable-LSE
Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 43 - 48

VLD2008-55
A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages
Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech)
pp. 49 - 54

VLD2008-56
Fast configuration experiments of a large-gates optically reconfigurable gate array
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
pp. 55 - 60

VLD2008-57
Fast dynamic optically reconfigurable gate array VLSI
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.)
pp. 61 - 66

VLD2008-58
A programmable multi-context optical reconfigurable gate array using a PAL-SLM
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
pp. 67 - 70

VLD2008-59
Variable linear transconductance OTA
Masaki Ikemoto, Cong-Kha Pham (UEC)
pp. 71 - 74

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan