IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 109, Number 11

Computer Systems

Workshop Date : 2009-04-21 / Issue Date : 2009-04-14

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Table of contents

CPSY2009-1
Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults
Hideo Kohinata, Kohei Marumoto, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
pp. 1 - 6

CPSY2009-2
A Development Process with A Model Checking Criterion
Michitaka Inui (Mitsubishi Electric Micro-Computer Application Software Corp.), Nobukazu Yoshioka (NII)
pp. 7 - 12

CPSY2009-3
Evaluation of a Metropolis Algorithm for Constructing Unstructured Overlay Networks
Tatsushi Takamura, Tatsuhiro Tsuchiya, Tohru Kikuno (Osaka Univ.)
pp. 13 - 17

CPSY2009-4
A Security Data-Flow Analysis in the Secure Software Development Environment DFITS
Fukutomo Nakanishi, Ryotaro Hayashi, Hiroyoshi Haruki, Yurie Fujimatsu, Mikio Hashimoto (Toshiba Corp.)
pp. 19 - 24

CPSY2009-5
Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units
Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.)
pp. 25 - 30

CPSY2009-6
[Invited Talk] Evolution and threat of botnet
Toshiaki Sudou (NTT Communications)
pp. 31 - 35

CPSY2009-7
A design of testable response analyzers in built-in self-test
Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 37 - 42

CPSY2009-8
Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design.
Daisuke Kozuwa, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.)
pp. 43 - 48

CPSY2009-9
Pulse Propagation Analysis for SER Evaluation of Logic Circuits
Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ)
pp. 49 - 54

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan