IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 110, Number 473

Computer Systems

Workshop Date : 2011-03-18 - 2011-03-19 / Issue Date : 2011-03-11

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Table of contents

CPSY2010-71
Examination of network fault detection method by use of AFM
Isao Shimokawa, Toshiaki Tarui, Hiroki Miyamoto, Tomohiro Baba (hitachi)
pp. 31 - 38

CPSY2010-72
Diagnosis for Automotive Electronic Control System -- Extraction of Singular Relation from CAN data with WPMax-SAT --
Shuichi Sato, Takuro Kutsuna (TCRDL), Naoya Chujo (AIT), Noriyoshi Sano (TCRDL)
pp. 39 - 44

CPSY2010-73
Development of a Network Recorder for High-Speed Real-Time Data Acquisition and Packet Capture
Kenji Toda, Mamoru Sekiyama (AIST)
pp. 45 - 50

CPSY2010-74
Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits
Nobutaka Kito (Kyoto Univ.), Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.)
pp. 51 - 56

CPSY2010-75
Design Method of Easily Testable Parallel Adders under Delay Constraints
Shinichi Fujii (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.)
pp. 57 - 62

CPSY2010-76
Virtual HILS -- Efficient software validation by entire system virtualization --
Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (HItachi)
pp. 243 - 247

CPSY2010-77
Performance Evaluation of High Performance Linpack on a Cell/B.E. Cluster with Heterogeneous Interconnect
Ryota Nishida, Tetsuya Nakahama, Toshiaki Kamata, Yuri Nishikawa, Hideharu Amano (Keio Univ.)
pp. 267 - 272

CPSY2010-78
Implementation and evaluation of Meresenne Twister with massive-parallel SIMD processing
Youhei Mochizuki, Naoyuki Yoshida, Naoki Matsumoto, Yuma Murakami, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ.)
pp. 273 - 278

CPSY2010-79
A study on parallel cryptographic processing with ultra-compact single-board computer
Takeshi Kumaki, Yuichiro Kurokawa, Takeshi Fujino (Ritsumeikan Univ.)
pp. 279 - 284

CPSY2010-80
Parallel C code generation from Simulink models
Takahiro Kumura (NEC/Osaka Univ.), Masato Edahiro, Yuichi Nakamura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 303 - 308

CPSY2010-81
An Architecture for Low-Latency Anonymizing Mechanism
Junichi Sawada, Koichi Inoue, Hiroaki Nishi (Keio Univ.)
pp. 309 - 314

CPSY2010-82
A Cache Control Method for Optimizing Receive Queue with Cache Injection
Ryota Mibu, Tomoyoshi Sugawara (NEC)
pp. 315 - 320

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan