Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2013-1
[Keynote Address]
Challenging Connect6 Hardware Design Competitions
Kentaro Sano (Tohoku Univ.)
pp. 1 - 6
RECONF2013-2
An FPGA Implementation of the Progressive Tree Neighborhood Algorithm
-- Phylogenetic Tree Reconstruction with Maximum Parsimony --
Henry Block, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 7 - 12
RECONF2013-3
Implementation and Evaluation of Data Compression Hardware for Bandwidth Enhancement of Multiple Data Streams
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 13 - 18
RECONF2013-4
FPGA Acceleration of Short Read Mapping
Yoko Sogabe, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 19 - 24
RECONF2013-5
Speed-up of Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.)
pp. 25 - 30
RECONF2013-6
Proposal of a Dependable Fine-grained Reconfigurable Device with ECC Technology
Yuki Yoshida, Kentaro Takaki, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN)
pp. 31 - 36
RECONF2013-7
An optically reconfigurable gate array using a temperature dependable holographic memory
Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.), Akifumi Ogiwara (Kobe City College of Tech.)
pp. 37 - 40
RECONF2013-8
Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis
Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 41 - 46
RECONF2013-9
[Invited Talk]
A Challenge of Acceleration of DA Algorithm by Parallel Processing
Michiaki Muraoka (Kochi Univ.)
p. 47
RECONF2013-10
Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication
Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 49 - 54
RECONF2013-11
Implementation of Speculative Gather System for CMA
Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano (Keio Univ.)
pp. 55 - 60
RECONF2013-12
Performance model evaluation for 3-D stencil computation using a high-level synthesis tool
Keisuke Dohi, Yoshihiro Nakamura, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 61 - 66
RECONF2013-13
A defect-robust FPGA-IP core architecture
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 67 - 72
RECONF2013-14
Video based real-time feature extraction and abnormal action detection on an FPGA
Kaoru Hamasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ)
pp. 73 - 78
RECONF2013-15
FAST COMPUTATION OF THE OPTICAL FLOW USING FPGA
Yu Tanabe, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 79 - 84
RECONF2013-16
An FPGA-based Sound Synthesizer and its GUI
Suguru Ochiai, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
pp. 85 - 90
RECONF2013-17
Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA
Yohei Hori, Toshihiro Katashita, Kazukuni Kobara (AIST)
pp. 91 - 96
RECONF2013-18
Study of Runtime Binary Acceleration on TCA node
Takaaki Miyajima, Takuya Kuhara (Keio Univ.), Toshihiro Hanawa (Univ. of Tsukuba), David Thomas (Imperial College), Hideharu Amano (Keio Univ.)
pp. 97 - 102
RECONF2013-19
The 3-D fluid computation on an FPGA system
Kenta Fujinami, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
pp. 103 - 108
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.