IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2014-05-29 / Issue Date : 2014-05-22

VLD2014-1
Analog Floorplan with Hierarchical Structure Constraints
Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 1 - 6

VLD2014-2
Characteristics of Programmable Delay Element based on Channel Decomposition
Daijiro Murooka, Koji Nagao, Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 7 - 12

VLD2014-3
A Subgradient Method for Analytical Minimization of Half-Perimeter Wirelength
Sohta Kayama, Hiroshi Miyashita (Univ. of Kitakyushu)
pp. 13 - 18

VLD2014-4
[Invited Talk] Multiple Patterning Lithography by Positive Semidefinite Relaxation
Tomomi Matsui (TITECH)
p. 19

VLD2014-5
Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model
Taichi Komine, Hiroshi Saito (Univ. of Aizu)
pp. 21 - 26

VLD2014-6
LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation
Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba)
pp. 27 - 32

VLD2014-7
Error Tolerance of Dual Pipeline Self Synchronous Circuits
Sai Denki, Makoto Ikeda (Univ. of Tokyo)
pp. 33 - 38

VLD2014-8
SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier
Masato Tamura, Makoto Ikeda (Univ. of Tokyo)
pp. 39 - 44

VLD2014-9
An Automatic Nested Loop Pipelining Method and Its Evaluation
Yusuke Nakatsuji, Masahiro Nambu, Takashi Kambe (Kinki Univ.)
pp. 57 - 62

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan