IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2014-06-11 - 2014-06-12 / Issue Date : 2014-06-04

RECONF2014-1
[Invited Talk] Prospects of Custom Accelerators for Large-Scale Computation -- Perspectives of Applications, Architectures, and Circuits --
Masanori Hariyama (Tohoku Univ.)
pp. 1 - 4

RECONF2014-2
A Dynamic Reconfigurable Mixed Analog-Digital Filter -- Applied to an Acoustic Diagnostic --
Hiroki Nakahara, Hideki Yoshida (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Renji Mikami (Mikami Consul.)
pp. 5 - 10

RECONF2014-3
Optimized HOG for database system
Mao Hatto, Takaaki Miyajima, Hiroki Matsutani, Hideharu Amano (Keio Univ.)
pp. 11 - 16

RECONF2014-4
Highly-Parallel FPGA Accelerator for DNA Sequence Alignment Using the Burrows-Wheeler Algorithm
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 17 - 20

RECONF2014-5
Improvement of Implementability by Exploring Routing Architecture in Flex Power FPGA
Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Hanpei Koike (AIST)
pp. 21 - 25

RECONF2014-6
An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 27 - 30

RECONF2014-7
Three-dimensional FPGA Structure using High-speed Serial Communication
Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 31 - 36

RECONF2014-8
Body bias control of low-power reconfigurable accelerator CMA-SOTB
Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.)
pp. 37 - 42

RECONF2014-9
A Design of Blokus Player Algorithm with Impulse High-Level Synthesis Tools
Ryo Kawai, Tomonori Izumi (Ritsumeikan Univ.)
pp. 43 - 47

RECONF2014-10
Zyndroid: HW/SW Coprocessing Platform for Android Applications
Susumu Mashimo, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 49 - 54

RECONF2014-11
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis
Koji Okina, Rie Soejima, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 55 - 60

RECONF2014-12
A Study on Accelerating Image Recognition Processing by HW/SW Cooperative Processing on an FPGA for Automatic Watch System on Navigation
Takeshi Ohkawa (Utsunomiya Univ.), Yohei Matsumoto (Tokyo Marine Univ.), Daichi Uetake, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 61 - 66

RECONF2014-13
Implementation of a RISC Processor with a Complex Instruction Accelerator -- Return to a CISC --
Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.)
pp. 67 - 72

RECONF2014-14
FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache
Kenji Kanazawa, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 73 - 78

RECONF2014-15
Design of an FPGA-Based Accelerator for Shortest-Path Search over Large-Scale Graphs
Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 79 - 83

RECONF2014-16
A software processor core with variable parallel execution
Takuya Nagashima, Shoji Tanabe, Yoshiki Yamaguchi (Univ. of Tsukuba)
pp. 85 - 90

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan