Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2012] | [2013] | [2014] | [2015] | [2016] | [2017] | [2018] | [Japanese] / [English]
CPSY2015-61
Performance Evaluations of Document-Oriented Databases using Remote GPU Cluster
Shin Morishima, Hiroki Matsutani (Keio Univ.)
pp. 1 - 6
CPSY2015-62
A study of GPU acceleration of "source" part in Hall-thruster simulation
Takaaki Miyajima, Shinatora Cho, Naoyuki Fujita (JAXA)
pp. 7 - 12
CPSY2015-63
Development and Evaluation of Simulator for Cellular Neural Network
Tomoya Kameda (NAIST), Mutsumi Kimura (Ryukoku Univ.), Yasuhiko Nakashima (NAIST)
pp. 13 - 17
CPSY2015-64
[Fellow Memorial Lecture]
Improving System Dependability by VLSI Test Technology
Seiji Kajihara (KIT)
pp. 19 - 20
CPSY2015-65
A C Framework for Integrating Algorithm Description and CGRA Implementation
Yasuhiko Nakashima (NAIST)
pp. 21 - 26
CPSY2015-66
Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM
Yuma Kikutani (OPUCT), Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)
pp. 27 - 32
CPSY2015-67
A proposal of the light field image compression and decompression using HEVC
Takamasa Mitani, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)
pp. 33 - 38
CPSY2015-68
A Preliminary Evaluation of Linear Network Using ThruChip Interface
Akio Nomura, Hiroki Matsutani, Yasuhiro Take (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Technology), Tadahiro Kuroda, Hideharu Amano (Keio Univ.)
pp. 39 - 44
CPSY2015-69
CSMA/CD and D-TDMA Hybrid Wireless 3D Bus Architecture
Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
pp. 45 - 50
CPSY2015-70
Performance Evaluation of K-best Viterbi Decoder for IoT Applications
Thi Hong Tran (NAIST), Dwi Rahma Ariyani, Lina Alfaridah ZH (Andalas Univ.), Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (NAIST)
pp. 51 - 56
CPSY2015-71
An implementation and preliminary evaluation of a dynamic body bias control scheme for a low power micro controller using SOTB MOSFET
Hayate Okuhara (Keio Univ.), Tomoaki Koide (UEC), Johannes maximilian kuehn, Akram Ben Ahmed (Keio Univ.), Koichiro Ishibashi (UEC), Hideharu Amano (Keio Univ.)
pp. 57 - 62
CPSY2015-72
Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment
Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.)
pp. 63 - 68
CPSY2015-73
Logic Design of A Single-Flux-Quantum Microprocessor
Koki Ishida, Tomonori Tsuhata (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.), Takatsugu Ono, Koji Inoue (Kyushu Univ.)
pp. 69 - 74
CPSY2015-74
Accuracy Analysis of Machine Learning based Performance Modeling for Microprocessors
Yoshihiro Tanaka, Takatsugu Ono, Koji Inoue (Kyushu Univ.)
pp. 75 - 80
CPSY2015-75
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II
Yusuke Hatori, Kohei Osawa (Keio Univ.), Keigo Mizotani (Nintendo), Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.)
pp. 81 - 86
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.