Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2012] | [2013] | [2014] | [2015] | [2016] | [2017] | [2018] | [Japanese] / [English]
DC2015-86
Note on Simultaneous Multiple Transient Fault Detection Based on Dual Approximate Logic
Keisuke Sonehara, Masayuki Arai (Nihon Univ.)
pp. 1 - 6
DC2015-87
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech)
pp. 7 - 12
DC2015-88
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value
Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 13 - 18
DC2015-89
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences
Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
pp. 19 - 24
DC2015-90
Delay fault injection framework based on logic simulation with zero delay model
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST)
pp. 25 - 30
DC2015-91
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis
Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Koji Yamazaki (Meiji Univ.)
pp. 31 - 36
DC2015-92
Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST)
pp. 37 - 42
DC2015-93
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns
Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU)
pp. 43 - 48
DC2015-94
Analog Circuit Design for a Precision Resistance Measurement of TSVs
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 49 - 54
DC2015-95
The Hybrid Communication Protocol for CANs
Koji Konomi, Muneyuki Nakamura, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
pp. 55 - 59
DC2015-96
Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 61 - 66
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.