Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2013] | [2014] | [2015] | [2016] | [2017] | [2018] | [2019] | [Japanese] / [English]
RECONF2016-24
Functional Improvement of cReComp Design Tool for Software-Component Generation of FPGA Processing
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 1 - 6
RECONF2016-25
(See Japanese page.)
pp. 7 - 12
RECONF2016-26
[Short Paper]
Study and Evaluation of FPGA based I/O Accelerator for the Flash Storage
Kazushi Nakagawa, Shotaro Shintani, Hirotoshi Akaike, Kentaro Shimada (Hitachi)
pp. 13 - 14
RECONF2016-27
The effect of the C ++ template meta-programming in high-level synthesis
Kenichiro Mitsuda, Owada Hiroshi, Shinji Yamamoto (ISP)
pp. 15 - 17
RECONF2016-28
(See Japanese page.)
pp. 19 - 22
RECONF2016-29
Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shoto Tamai (Oi Electric), Takumi Sato (Shonan Inst. of Tech.)
pp. 23 - 28
RECONF2016-30
Tomohiro Tanaka, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (Taiyo Yuden)
pp. 29 - 34
RECONF2016-31
[Invited Talk]
Verification and Debugging Support Techniques for High-Level Designs
Takeshi Matsumoto (INCT)
p. 35
RECONF2016-32
[Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)
p. 37
RECONF2016-33
Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board
Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science)
pp. 39 - 44
RECONF2016-34
A Study of Methodology and Tools for Open-source FPGA Accelerators
Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 45 - 50
RECONF2016-35
(See Japanese page.)
pp. 51 - 56
RECONF2016-36
A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL
Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, Shinpei Sato (TITECH), Naoya Maruyama (RIKEN)
pp. 57 - 62
RECONF2016-37
A Memory Based Realization of the Binarized Deep Convolutional Neural Network
Hiroki Nakahara, Haruyoshi Yonekawa (TITECH), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (Poco a poco Networks), Masato Motomura (Hokkaido Univ.)
pp. 63 - 68
RECONF2016-38
An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation
Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.)
pp. 69 - 74
RECONF2016-39
(See Japanese page.)
pp. 75 - 80
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.